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[PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
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From: |
LIU Zhiwei |
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Subject: |
[PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU |
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Date: |
Mon, 1 Jul 2024 11:37:19 +0800 |
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6fe0d712b4..36a712044a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -668,8 +668,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
#ifdef CONFIG_USER_ONLY
return env->misa_mxl;
#else
- return get_field(env->mstatus, MSTATUS64_SXL);
+ if (env->misa_mxl != MXL_RV32) {
+ return get_field(env->mstatus, MSTATUS64_SXL);
+ }
#endif
+ return MXL_RV32;
}
#endif
--
2.43.0
- [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU, LIU Zhiwei, 2024/06/30
- [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI, LIU Zhiwei, 2024/06/30
- [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32, LIU Zhiwei, 2024/06/30
- [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU,
LIU Zhiwei <=
- [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64, LIU Zhiwei, 2024/06/30
- [PATCH 5/6] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU, LIU Zhiwei, 2024/06/30
- [PATCH 6/6] target/riscv: Enable RV32 CPU support in RV64 QEMU, LIU Zhiwei, 2024/06/30