Re: [PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV3

qemu-riscv

From:	Richard Henderson
Subject:	Re: [PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
Date:	Wed, 3 Jul 2024 09:49:19 -0700
User-agent:	Mozilla Thunderbird

On 7/3/24 07:49, LIU Zhiwei wrote:

+        sxlen = 16UL << riscv_cpu_sxl(env);


As before, drop UL.


r~

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[PATCH v3 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI, LIU Zhiwei, 2024/07/03
- [PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32, LIU Zhiwei, 2024/07/03
  - Re: [PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32, Richard Henderson, 2024/07/03
- [PATCH v3 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64, LIU Zhiwei, 2024/07/03
- [PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/03
  - Re: [PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU, Richard Henderson <=
- [PATCH v3 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU, LIU Zhiwei, 2024/07/03
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