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[PATCH v5 13/15] target/riscv: compressed encodings for sspush and sspop
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From: |
Deepak Gupta |
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Subject: |
[PATCH v5 13/15] target/riscv: compressed encodings for sspush and sspopchk |
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Date: |
Mon, 19 Aug 2024 17:01:27 -0700 |
sspush/sspopchk have compressed encodings carved out of zcmops.
compressed sspush is designated as c.mop.1 while compressed sspopchk
is designated as c.mop.5.
Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
c.sspopchk x5 exists while c.sspopchk x1 doesn't.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
---
target/riscv/insn16.decode | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 3953bcf82d..bf893d1c2e 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -140,6 +140,10 @@ sw 110 ... ... .. ... 00 @cs_w
addi 000 . ..... ..... 01 @ci
addi 010 . ..... ..... 01 @c_li
{
+ # c.sspush x1 carving out of zcmops
+ sspush 011 0 00001 00000 01 &r2_s rs2=1 rs1=0
+ # c.sspopchk x5 carving out of zcmops
+ sspopchk 011 0 00101 00000 01 &r2 rs1=5 rd=0
c_mop_n 011 0 0 n:3 1 00000 01
illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
addi 011 . 00010 ..... 01 @c_addi16sp
--
2.44.0
- [PATCH v5 04/15] target/riscv: additional code information for sw check, (continued)
- [PATCH v5 04/15] target/riscv: additional code information for sw check, Deepak Gupta, 2024/08/19
- [PATCH v5 01/15] target/riscv: Add zicfilp extension, Deepak Gupta, 2024/08/19
- [PATCH v5 03/15] target/riscv: save and restore elp state on priv transitions, Deepak Gupta, 2024/08/19
- [PATCH v5 08/15] target/riscv: Add zicfiss extension, Deepak Gupta, 2024/08/19
- [PATCH v5 10/15] target/riscv: tb flag for shadow stack instructions, Deepak Gupta, 2024/08/19
- [PATCH v5 12/15] target/riscv: implement zicfiss instructions, Deepak Gupta, 2024/08/19
- [PATCH v5 06/15] target/riscv: zicfilp `lpad` impl and branch tracking, Deepak Gupta, 2024/08/19
- [PATCH v5 05/15] target/riscv: tracking indirect branches (fcfi) for zicfilp, Deepak Gupta, 2024/08/19
- [PATCH v5 07/15] disas/riscv: enable `lpad` disassembly, Deepak Gupta, 2024/08/19
- [PATCH v5 13/15] target/riscv: compressed encodings for sspush and sspopchk,
Deepak Gupta <=
- [PATCH v5 15/15] disas/riscv: enable disassembly for compressed sspush/sspopchk, Deepak Gupta, 2024/08/19
- [PATCH v5 11/15] target/riscv: mmu changes for zicfiss shadow stack protection, Deepak Gupta, 2024/08/19
[PATCH v5 14/15] disas/riscv: enable disassembly for zicfiss instructions, Deepak Gupta, 2024/08/19
[PATCH v5 09/15] target/riscv: introduce ssp and enabling controls for zicfiss, Deepak Gupta, 2024/08/19