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[PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults
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From: |
Deepak Gupta |
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Subject: |
[PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg |
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Date: |
Tue, 27 Aug 2024 16:18:46 -0700 |
set priv to be PRV_U for qemu-user on riscv. And set default value for
*envcfg CSR.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
linux-user/riscv/cpu_loop.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 52c49c2e42..7a68e8717b 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -32,6 +32,10 @@ void cpu_loop(CPURISCVState *env)
int trapnr;
target_ulong ret;
+ env->priv = PRV_U;
+ env->senvcfg = 0;
+ env->menvcfg = 0;
+
for (;;) {
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
--
2.44.0
- [PATCH v10 00/21] riscv support for control flow integrity extensions, Deepak Gupta, 2024/08/27
- [PATCH v10 07/21] target/riscv: tracking indirect branches (fcfi) for zicfilp, Deepak Gupta, 2024/08/27
- [PATCH v10 09/21] disas/riscv: enable `lpad` disassembly, Deepak Gupta, 2024/08/27
- [PATCH v10 05/21] target/riscv: save and restore elp state on priv transitions, Deepak Gupta, 2024/08/27
- [PATCH v10 06/21] target/riscv: additional code information for sw check, Deepak Gupta, 2024/08/27
- [PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property, Deepak Gupta, 2024/08/27
- [PATCH v10 08/21] target/riscv: zicfilp `lpad` impl and branch tracking, Deepak Gupta, 2024/08/27