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Re: [PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native |
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Date: |
Thu, 29 Aug 2024 09:35:15 +1000 |
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User-agent: |
Mozilla Thunderbird |
On 8/27/24 18:31, LIU Zhiwei wrote:
We will use this one. But probe the vlen in util/cpuinfo-riscv.c has no meaning as we
sometimes use the compiler settings or hw_probe API. In these cases, the vlen detected in
util/cpuinfo-riscv.c is zero.
Pardon?
While you might check __riscv_zve64x at compile-time, you would still fall
through to
---
}
+ if (info & CPUINFO_ZVE64X) {
+ unsigned long vl;
+ asm("vsetvli %0, r0, e64" : "=r"(vl));
+ if (vl) {
+ riscv_vlen = vl * 8;
+ } else {
+ info &= ~CPUINFO_ZVE64X;
+ }
+ }
+
info |= CPUINFO_ALWAYS;
cpuinfo = info;
---
Do not attempt to merge the vsetvli from the SIGILL probe; I expect that path to become
unused and eventually vanish.
r~
- Re: [PATCH v1 10/15] tcg/riscv: Implement vector not/neg ops, (continued)
- [PATCH v1 11/15] tcg/riscv: Implement vector sat/mul ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 12/15] tcg/riscv: Implement vector min/max ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 13/15] tcg/riscv: Implement vector shs/v ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native, LIU Zhiwei, 2024/08/13