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[PATCH v4 09/11] target/riscv: Invoke pmu init after feature enable
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From: |
Atish Patra |
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Subject: |
[PATCH v4 09/11] target/riscv: Invoke pmu init after feature enable |
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Date: |
Tue, 03 Dec 2024 15:14:47 -0800 |
The dependant ISA features are enabled at the end of cpu_realize
in finalize_features. Thus, PMU init should be invoked after that
only. Move the init invocation to riscv_tcg_cpu_finalize_features.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c62c2216961b..2b57aa4d1704 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -934,6 +934,20 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error
**errp)
error_propagate(errp, local_err);
return;
}
+#ifndef CONFIG_USER_ONLY
+ if (cpu->cfg.pmu_mask) {
+ riscv_pmu_init(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (cpu->cfg.ext_sscofpmf) {
+ cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ riscv_pmu_timer_cb, cpu);
+ }
+ }
+#endif
}
void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
@@ -981,7 +995,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
**errp)
#ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env;
- Error *local_err = NULL;
tcg_cflags_set(CPU(cs), CF_PCREL);
@@ -989,19 +1002,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
**errp)
riscv_timer_init(cpu);
}
- if (cpu->cfg.pmu_mask) {
- riscv_pmu_init(cpu, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return false;
- }
-
- if (cpu->cfg.ext_sscofpmf) {
- cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- riscv_pmu_timer_cb, cpu);
- }
- }
-
/* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */
if (riscv_has_ext(env, RVH)) {
env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP;
--
2.34.1
- [PATCH v4 01/11] target/riscv: Add properties for Indirect CSR Access extension, (continued)
- [PATCH v4 01/11] target/riscv: Add properties for Indirect CSR Access extension, Atish Patra, 2024/12/03
- [PATCH v4 02/11] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2024/12/03
- [PATCH v4 04/11] target/riscv: Support generic CSR indirect access, Atish Patra, 2024/12/03
- [PATCH v4 03/11] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2024/12/03
- [PATCH v4 05/11] target/riscv: Add properties for counter delegation ISA extensions, Atish Patra, 2024/12/03
- [PATCH v4 06/11] target/riscv: Add counter delegation definitions, Atish Patra, 2024/12/03
- [PATCH v4 07/11] target/riscv: Add select value range check for counter delegation, Atish Patra, 2024/12/03
- [PATCH v4 08/11] target/riscv: Add counter delegation/configuration support, Atish Patra, 2024/12/03
- [PATCH v4 09/11] target/riscv: Invoke pmu init after feature enable,
Atish Patra <=
- [PATCH v4 10/11] target/riscv: Add implied rule for counter delegation extensions, Atish Patra, 2024/12/03
- [PATCH v4 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Atish Patra, 2024/12/03