[PATCH v3] riscv/gdb: add V bit to priv register

[Yanfeng Liu]

This adds virtualization mode (V bit) as bit(2) of register `priv`
per RiscV debug spec v1.0.0-rc3. Checked with gdb-multiarch v12.1.

Note that GDB may display `INVALID` tag for the value when V bit
is set, this doesn't affect accessing to the bit.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
---
 target/riscv/gdbstub.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index c07df972f1..8cc095cda3 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -213,7 +213,10 @@ static int riscv_gdb_get_virtual(CPUState *cs, GByteArray 
*buf, int n)
         RISCVCPU *cpu = RISCV_CPU(cs);
         CPURISCVState *env = &cpu->env;
 
-        return gdb_get_regl(buf, env->priv);
+        /* Per RiscV debug spec v1.0.0 rc3 */
+        target_ulong vbit = (env->virt_enabled) ? BIT(2) : 0;
+
+        return gdb_get_regl(buf, env->priv | vbit);
 #endif
     }
     return 0;
@@ -230,6 +233,8 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t 
*mem_buf, int n)
         if (env->priv == PRV_RESERVED) {
             env->priv = PRV_S;
         }
+        env->virt_enabled = (env->priv == PRV_M) ? 0 :
+                            ((ldtul_p(mem_buf) & BIT(2)) >> 2);
 #endif
         return sizeof(target_ulong);
     }
-- 
2.34.1