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RE: [avr-gcc-list] Missing compiler optimizations?


From: Nigel Winterbottom
Subject: RE: [avr-gcc-list] Missing compiler optimizations?
Date: Tue, 24 Jan 2006 21:38:15 -0000

Erik Walthinsen wrote:

> That's true, but the compiler could use the high registers and save them 
> with the same or slightly more push/pops around the called functions, 

OK, you obviously do know about avr-gcc register useage and I missed the caller 
/callee difference.

What sparked my response was the fact that in your hand written code (pasted 
below) you haven't stacked "caller saves" registers around your function call.


[Erik Walthinsen code:]

By hand, I get:

.global load_eeprom_defaults_asm
load_eeprom_defaults_asm:
/* Registers:
        r31:r30         ram address
        r27:r26         eeprom address
        r25:r24         eeprom_read_byte address argument
        r24             eeprom read byte
        r23             i (port)
*/
        ldi r26, lo8(0)         /* load zero EEPROM address */
        ldi r27, hi8(0)

/* load the pinconfig array */
        ldi r30, lo8(pinconfig) /* load Z with pinconfig */
        ldi r31, hi8(pinconfig)
        ldi r23, PARTPINS       /* start loop with PARTPINS */
pinconfigLoop:
        movw r24, r26           /* copy EEPROM addr to argument */
        rcall eeprom_read_byte
        st Z+, r24              /* store the result in pinconfig[] */
        adiw r26, 1             /* increment the EEPROM addr */
        dec r23                 /* decrement pin count */
        brne pinconfigLoop      /* ...and loop */

        ret

[\Erik Walthinsen code:]


BTW I found this compiler flag in the avr-gcc manual.

−fcaller-saves
Enable values to be allocated in registers that will be clobbered by function 
calls, by emitting extra
instructions to save and restore the registers around such calls. Such 
allocation is done only when it
seems to result in better code than would otherwise be produced.
This option is always enabled by default on certain machines, usually those 
which have no call-preserved
registers to use instead.
For all machines, optimization level 2 and higher enables this flag by default.


Regards

Nigel Winterbottom






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