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[avr-gcc-list] Inversion of logic improves size speed
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From: |
Wouter van Gulik |
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Subject: |
[avr-gcc-list] Inversion of logic improves size speed |
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Date: |
Sun, 5 Aug 2007 21:46:39 +0200 |
Hi list,
After some testing I found out that inverting shift and and instruction can
significantly reduce speed and size.
In the first is case the compiler misses that it can optimise the shifts for
bit 4..7 by first nibble swapping.
Which it does figure out when rewriting the part as in the lower part.
Is this a (known?) bug or am I missing something?
Wouter
/* This results in shifting instructions */
uint8_t getBit0(uint8_t temp) { uint8_t r = 0; if(temp&(1<<0)) r|=0x1;
return r; }
uint8_t getBit1(uint8_t temp) { uint8_t r = 0; if(temp&(1<<1)) r|=0x1;
return r; }
uint8_t getBit2(uint8_t temp) { uint8_t r = 0; if(temp&(1<<2)) r|=0x1;
return r; }
uint8_t getBit3(uint8_t temp) { uint8_t r = 0; if(temp&(1<<3)) r|=0x1;
return r; }
uint8_t getBit4(uint8_t temp) { uint8_t r = 0; if(temp&(1<<4)) r|=0x1;
return r; }
uint8_t getBit5(uint8_t temp) { uint8_t r = 0; if(temp&(1<<5)) r|=0x1;
return r; }
uint8_t getBit6(uint8_t temp) { uint8_t r = 0; if(temp&(1<<6)) r|=0x1;
return r; }
uint8_t getBit7(uint8_t temp) { uint8_t r = 0; if(temp&(1<<7)) r|=0x1;
return r; }
/* This results in better shifting instructions */
uint8_t getBit0InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>0)&1)
r|=0x1; return r; }
uint8_t getBit1InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>1)&1)
r|=0x1; return r; }
uint8_t getBit2InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>2)&1)
r|=0x1; return r; }
uint8_t getBit3InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>3)&1)
r|=0x1; return r; }
uint8_t getBit4InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>4)&1)
r|=0x1; return r; }
uint8_t getBit5InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>5)&1)
r|=0x1; return r; }
uint8_t getBit6InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>6)&1)
r|=0x1; return r; }
uint8_t getBit7InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>7)&1)
r|=0x1; return r; }
This results in:
/* This results in shifting instructions */
uint8_t getBit0(uint8_t temp) { uint8_t r = 0; if(temp&(1<<0)) r|=0x1;
return r; }
ae: 81 70 andi r24, 0x01 ; 1
b0: 99 27 eor r25, r25
b2: 08 95 ret
000000b4 <getBit1>:
uint8_t getBit1(uint8_t temp) { uint8_t r = 0; if(temp&(1<<1)) r|=0x1;
return r; }
b4: 99 27 eor r25, r25
b6: 96 95 lsr r25
b8: 87 95 ror r24
ba: 81 70 andi r24, 0x01 ; 1
bc: 90 70 andi r25, 0x00 ; 0
be: 08 95 ret
000000c0 <getBit2>:
uint8_t getBit2(uint8_t temp) { uint8_t r = 0; if(temp&(1<<2)) r|=0x1;
return r; }
c0: 99 27 eor r25, r25
c2: 96 95 lsr r25
c4: 87 95 ror r24
c6: 96 95 lsr r25
c8: 87 95 ror r24
ca: 81 70 andi r24, 0x01 ; 1
cc: 90 70 andi r25, 0x00 ; 0
ce: 08 95 ret
000000d0 <getBit3>:
uint8_t getBit3(uint8_t temp) { uint8_t r = 0; if(temp&(1<<3)) r|=0x1;
return r; }
d0: 99 27 eor r25, r25
d2: 43 e0 ldi r20, 0x03 ; 3
d4: 96 95 lsr r25
d6: 87 95 ror r24
d8: 4a 95 dec r20
da: e1 f7 brne .-8 ; 0xd4 <getBit3+0x4>
dc: 81 70 andi r24, 0x01 ; 1
de: 90 70 andi r25, 0x00 ; 0
e0: 08 95 ret
000000e2 <getBit4>:
uint8_t getBit4(uint8_t temp) { uint8_t r = 0; if(temp&(1<<4)) r|=0x1;
return r; }
e2: 99 27 eor r25, r25
e4: 54 e0 ldi r21, 0x04 ; 4
e6: 96 95 lsr r25
e8: 87 95 ror r24
ea: 5a 95 dec r21
ec: e1 f7 brne .-8 ; 0xe6 <getBit4+0x4>
ee: 81 70 andi r24, 0x01 ; 1
f0: 90 70 andi r25, 0x00 ; 0
f2: 08 95 ret
000000f4 <getBit5>:
uint8_t getBit5(uint8_t temp) { uint8_t r = 0; if(temp&(1<<5)) r|=0x1;
return r; }
f4: 99 27 eor r25, r25
f6: 65 e0 ldi r22, 0x05 ; 5
f8: 96 95 lsr r25
fa: 87 95 ror r24
fc: 6a 95 dec r22
fe: e1 f7 brne .-8 ; 0xf8 <getBit5+0x4>
100: 81 70 andi r24, 0x01 ; 1
102: 90 70 andi r25, 0x00 ; 0
104: 08 95 ret
00000106 <getBit6>:
uint8_t getBit6(uint8_t temp) { uint8_t r = 0; if(temp&(1<<6)) r|=0x1;
return r; }
106: 99 27 eor r25, r25
108: 76 e0 ldi r23, 0x06 ; 6
10a: 96 95 lsr r25
10c: 87 95 ror r24
10e: 7a 95 dec r23
110: e1 f7 brne .-8 ; 0x10a <getBit6+0x4>
112: 81 70 andi r24, 0x01 ; 1
114: 90 70 andi r25, 0x00 ; 0
116: 08 95 ret
00000118 <getBit7>:
uint8_t getBit7(uint8_t temp) { uint8_t r = 0; if(temp&(1<<7)) r|=0x1;
return r; }
118: 88 1f adc r24, r24
11a: 88 27 eor r24, r24
11c: 88 1f adc r24, r24
11e: 99 27 eor r25, r25
120: 08 95 ret
00000122 <getBit0InvShift>:
/* This results in shifting instructions */
uint8_t getBit0InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>0)&1)
r|=0x1; return r; }
122: 81 70 andi r24, 0x01 ; 1
124: 99 27 eor r25, r25
126: 08 95 ret
00000128 <getBit1InvShift>:
uint8_t getBit1InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>1)&1)
r|=0x1; return r; }
128: 86 95 lsr r24
12a: 81 70 andi r24, 0x01 ; 1
12c: 99 27 eor r25, r25
12e: 08 95 ret
00000130 <getBit2InvShift>:
uint8_t getBit2InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>2)&1)
r|=0x1; return r; }
130: 86 95 lsr r24
132: 86 95 lsr r24
134: 81 70 andi r24, 0x01 ; 1
136: 99 27 eor r25, r25
138: 08 95 ret
0000013a <getBit3InvShift>:
uint8_t getBit3InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>3)&1)
r|=0x1; return r; }
13a: 86 95 lsr r24
13c: 86 95 lsr r24
13e: 86 95 lsr r24
140: 81 70 andi r24, 0x01 ; 1
142: 99 27 eor r25, r25
144: 08 95 ret
00000146 <getBit4InvShift>:
uint8_t getBit4InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>4)&1)
r|=0x1; return r; }
146: 82 95 swap r24
148: 8f 70 andi r24, 0x0F ; 15
14a: 81 70 andi r24, 0x01 ; 1
14c: 99 27 eor r25, r25
14e: 08 95 ret
00000150 <getBit5InvShift>:
uint8_t getBit5InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>5)&1)
r|=0x1; return r; }
150: 82 95 swap r24
152: 86 95 lsr r24
154: 87 70 andi r24, 0x07 ; 7
156: 81 70 andi r24, 0x01 ; 1
158: 99 27 eor r25, r25
15a: 08 95 ret
0000015c <getBit6InvShift>:
uint8_t getBit6InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>6)&1)
r|=0x1; return r; }
15c: 82 95 swap r24
15e: 86 95 lsr r24
160: 86 95 lsr r24
162: 83 70 andi r24, 0x03 ; 3
164: 81 70 andi r24, 0x01 ; 1
166: 99 27 eor r25, r25
168: 08 95 ret
0000016a <getBit7InvShift>:
uint8_t getBit7InvShift(uint8_t temp) { uint8_t r = 0; if((temp>>7)&1)
r|=0x1; return r; }
16a: 88 1f adc r24, r24
16c: 88 27 eor r24, r24
16e: 88 1f adc r24, r24
170: 99 27 eor r25, r25
172: 08 95 ret
- [avr-gcc-list] Inversion of logic improves size speed,
Wouter van Gulik <=
- Re: [avr-gcc-list] Inversion of logic improves size speed, Joerg Wunsch, 2007/08/06
- Re: [avr-gcc-list] Inversion of logic improves size speed, Anatoly Sokolov, 2007/08/26
- Re: [avr-gcc-list] Inversion of logic improves size speed, Anatoly Sokolov, 2007/08/27
- RE: [avr-gcc-list] Inversion of logic improves size speed, Eric Weddington, 2007/08/27
- RE: [avr-gcc-list] Inversion of logic improves size speed, Eric Weddington, 2007/08/28