[Commit-gnuradio] [gnuradio] 50/148: make the testbench work in this environment, without the crossclock settings bus

[git]

This is an automated email from the git hooks/post-receive script.

nwest pushed a commit to annotated tag old_usrp_devel_udp
in repository gnuradio.

commit 0bf3697eacca5c8a7c8f7c6a325ac1f1eb0acc09
Author: Matt Ettus <address@hidden>
Date:   Tue Dec 8 22:58:49 2009 -0800

    make the testbench work in this environment, without the crossclock 
settings bus
---
 usrp2/fpga/vrt/.gitignore    |  1 +
 usrp2/fpga/vrt/vita_rx.build |  2 +-
 usrp2/fpga/vrt/vita_rx_tb.v  | 10 ++++++----
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/usrp2/fpga/vrt/.gitignore b/usrp2/fpga/vrt/.gitignore
index 14460fb..560066d 100644
--- a/usrp2/fpga/vrt/.gitignore
+++ b/usrp2/fpga/vrt/.gitignore
@@ -1,2 +1,3 @@
 vita_rx_tb
+vita_tx_tb
 *.vcd
diff --git a/usrp2/fpga/vrt/vita_rx.build b/usrp2/fpga/vrt/vita_rx.build
index e25e1b4..f6d2d75 100755
--- a/usrp2/fpga/vrt/vita_rx.build
+++ b/usrp2/fpga/vrt/vita_rx.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y 
../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y 
/opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb 
vita_rx_tb.v
+iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y 
../control_lib/newfifo -y ../coregen -y 
/opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y 
/opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb 
vita_rx_tb.v
diff --git a/usrp2/fpga/vrt/vita_rx_tb.v b/usrp2/fpga/vrt/vita_rx_tb.v
index bc62c68..b4fda96 100644
--- a/usrp2/fpga/vrt/vita_rx_tb.v
+++ b/usrp2/fpga/vrt/vita_rx_tb.v
@@ -29,24 +29,26 @@ module vita_rx_tb;
    wire [7:0]  set_addr_dsp;
    wire [31:0] set_data_dsp;
 
+   /*
    settings_bus_crossclock settings_bus_xclk_dsp
      (.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr), 
.set_data_i(set_data),
       .clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp), 
.set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
-      
+    */
+   
    wire        sample_dst_rdy, sample_src_rdy;
    //wire [99:0] sample_data_o;
    wire [64+4+(MAXCHAN*32)-1:0] sample_data_o;
 
    vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
      (.clk(clk), .reset(reset), .clear(0),
-      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .vita_time(vita_time), .overrun(overrun),
       .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), 
.sample_fifo_src_rdy_o(sample_src_rdy),
       .sample(sample), .run(run), .strobe(strobe));
 
    vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer
      (.clk(clk), .reset(reset), .clear(0),
-      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy),
       .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), 
.sample_fifo_src_rdy_i(sample_src_rdy),
       .fifo_occupied(), .fifo_full(), .fifo_empty() );
@@ -61,7 +63,7 @@ module vita_rx_tb;
    
    time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit
      (.clk(clk), .rst(reset),
-      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .pps(0), .vita_time(vita_time));
    
    always @(posedge clk)