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[Commit-gnuradio] [gnuradio] 19/148: VITA49 rx (and tx skeleton) copied
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[Commit-gnuradio] [gnuradio] 19/148: VITA49 rx (and tx skeleton) copied over from quad radio |
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Date: |
Mon, 15 Aug 2016 00:47:20 +0000 (UTC) |
This is an automated email from the git hooks/post-receive script.
nwest pushed a commit to annotated tag old_usrp_devel_udp
in repository gnuradio.
commit c597ff1be542ba50a5c01045748b5d474c1b09e2
Author: Matt Ettus <address@hidden>
Date: Thu Nov 5 12:03:47 2009 -0800
VITA49 rx (and tx skeleton) copied over from quad radio
---
usrp2/fpga/vrt/.gitignore | 2 +
usrp2/fpga/vrt/vita_rx.build | 1 +
usrp2/fpga/vrt/vita_rx_control.v | 174 ++++++++++++++++++++++++
usrp2/fpga/vrt/vita_rx_framer.v | 195 +++++++++++++++++++++++++++
usrp2/fpga/vrt/vita_rx_tb.v | 211 ++++++++++++++++++++++++++++++
usrp2/fpga/vrt/vita_tx_control.v | 174 ++++++++++++++++++++++++
usrp2/fpga/vrt/vita_tx_deframer.v | 269 ++++++++++++++++++++++++++++++++++++++
7 files changed, 1026 insertions(+)
diff --git a/usrp2/fpga/vrt/.gitignore b/usrp2/fpga/vrt/.gitignore
new file mode 100644
index 0000000..14460fb
--- /dev/null
+++ b/usrp2/fpga/vrt/.gitignore
@@ -0,0 +1,2 @@
+vita_rx_tb
+*.vcd
diff --git a/usrp2/fpga/vrt/vita_rx.build b/usrp2/fpga/vrt/vita_rx.build
new file mode 100755
index 0000000..e25e1b4
--- /dev/null
+++ b/usrp2/fpga/vrt/vita_rx.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y
../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y
/opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb
vita_rx_tb.v
diff --git a/usrp2/fpga/vrt/vita_rx_control.v b/usrp2/fpga/vrt/vita_rx_control.v
new file mode 100644
index 0000000..2e96e6d
--- /dev/null
+++ b/usrp2/fpga/vrt/vita_rx_control.v
@@ -0,0 +1,174 @@
+
+module vita_rx_control
+ #(parameter BASE=0,
+ parameter WIDTH=32)
+ (input clk, input reset, input clear,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ input [63:0] vita_time,
+ output overrun,
+
+ // To vita_rx_framer
+ output [4+64+WIDTH-1:0] sample_fifo_o,
+ output sample_fifo_src_rdy_o,
+ input sample_fifo_dst_rdy_i,
+
+ // From DSP Core
+ input [WIDTH-1:0] sample,
+ output run,
+ input strobe,
+
+ output [31:0] debug_rx
+ );
+
+ // FIXME add TX Interruption (halt, pause, continue) functionality
+
+ wire [63:0] new_time;
+ wire [31:0] new_command;
+ wire sc_pre1, clear_int, clear_reg;
+
+ assign clear_int = clear | clear_reg;
+
+ wire [63:0] rcvtime_pre;
+ reg [63:0] rcvtime;
+ wire [29:0] numlines_pre;
+ wire send_imm_pre, chain_pre;
+ reg send_imm, chain;
+ wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
+ reg sc_pre2;
+ wire [33:0] fifo_line;
+ reg [29:0] lines_left;
+ reg [2:0] ibs_state;
+ wire now, early, late;
+ wire sample_fifo_in_rdy;
+
+ setting_reg #(.my_addr(BASE)) sr_cmd
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(new_command),.changed());
+
+ setting_reg #(.my_addr(BASE+1)) sr_time_h
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(new_time[63:32]),.changed());
+
+ setting_reg #(.my_addr(BASE+2)) sr_time_l
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(new_time[31:0]),.changed(sc_pre1));
+
+ setting_reg #(.my_addr(BASE+3)) sr_clear
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(),.changed(clear_reg));
+
+ // FIFO to store commands sent from the settings bus
+ always @(posedge clk)
+ sc_pre2 <= sc_pre1;
+ assign write_ctrl = sc_pre1 & ~sc_pre2;
+
+ wire [4:0] command_queue_len;
+ shortfifo #(.WIDTH(96)) commandfifo
+ (.clk(clk),.rst(reset),.clear(clear_int),
+ .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl),
.full(full_ctrl),
+ .dataout({send_imm_pre,chain_pre,numlines_pre,rcvtime_pre}),
+ .read(read_ctrl), .empty(empty_ctrl),
+ .occupied(command_queue_len), .space() );
+
+ reg [33:0] pkt_fifo_line;
+
+ localparam IBS_IDLE = 0;
+ localparam IBS_WAITING = 1;
+ localparam IBS_RUNNING = 2;
+ localparam IBS_OVERRUN = 4;
+ localparam IBS_BROKENCHAIN = 5;
+ localparam IBS_LATECMD = 6;
+
+ wire signal_cmd_done = (lines_left == 1) & (~chain | (~empty_ctrl &
(numlines_pre==0)));
+ wire signal_overrun = (ibs_state == IBS_OVERRUN);
+ wire signal_brokenchain = (ibs_state == IBS_BROKENCHAIN);
+ wire signal_latecmd = (ibs_state == IBS_LATECMD);
+
+ // Buffer of samples for while we're writing the packet headers
+ wire [3:0] flags =
{signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+
+ wire attempt_sample_write = ((run & strobe) |
(ibs_state==IBS_OVERRUN) |
+ (ibs_state==IBS_BROKENCHAIN) |
(ibs_state==IBS_LATECMD));
+
+ fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo
+ (.clk(clk),.reset(reset),.clear(clear_int),
+ .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write),
.dst_rdy_o(sample_fifo_in_rdy),
+ .dataout(sample_fifo_o),
+ .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i),
+ .space(), .occupied() );
+
+ // Inband Signalling State Machine
+ time_compare
+ time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now),
.early(early), .late(late));
+
+ wire too_late = late & ~send_imm;
+ wire go_now = now | send_imm;
+ wire full = ~sample_fifo_in_rdy;
+
+ always @(posedge clk)
+ if(reset | clear_int)
+ begin
+ ibs_state <= IBS_IDLE;
+ lines_left <= 0;
+ rcvtime <= 0;
+ send_imm <= 0;
+ chain <= 0;
+ end
+ else
+ case(ibs_state)
+ IBS_IDLE :
+ if(~empty_ctrl)
+ begin
+ lines_left <= numlines_pre;
+ rcvtime <= rcvtime_pre;
+ ibs_state <= IBS_WAITING;
+ send_imm <= send_imm_pre;
+ chain <= chain_pre;
+ end
+ IBS_WAITING :
+ if(go_now)
+ ibs_state <= IBS_RUNNING;
+ else if(too_late)
+ ibs_state <= IBS_LATECMD;
+ IBS_RUNNING :
+ if(strobe)
+ if(full)
+ ibs_state <= IBS_OVERRUN;
+ else
+ begin
+ lines_left <= lines_left - 1;
+ if(lines_left == 1)
+ if(~chain)
+ ibs_state <= IBS_IDLE;
+ else if(empty_ctrl)
+ ibs_state <= IBS_BROKENCHAIN;
+ else
+ begin
+ lines_left <= numlines_pre;
+ rcvtime <= rcvtime_pre;
+ send_imm <= send_imm_pre;
+ chain <= chain_pre;
+ if(numlines_pre == 0) // If we are told to stop here
+ ibs_state <= IBS_IDLE;
+ else
+ ibs_state <= IBS_RUNNING;
+ end
+ end // else: !if(full)
+ IBS_OVERRUN, IBS_LATECMD, IBS_BROKENCHAIN :
+ if(sample_fifo_in_rdy)
+ ibs_state <= IBS_IDLE;
+ endcase // case(ibs_state)
+
+ assign overrun = (ibs_state == IBS_OVERRUN);
+ assign run = (ibs_state == IBS_RUNNING);
+
+ assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING)
& strobe & ~full & (lines_left==1) & chain) )
+ & ~empty_ctrl;
+
+ assign debug_rx = { { ibs_state[2:0], command_queue_len },
+ { 8'd0 },
+ { go_now, too_late, run, strobe, read_ctrl, write_ctrl,
full_ctrl, empty_ctrl },
+ { 2'b0, overrun, chain_pre, sample_fifo_in_rdy,
attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
+
+endmodule // rx_control
diff --git a/usrp2/fpga/vrt/vita_rx_framer.v b/usrp2/fpga/vrt/vita_rx_framer.v
new file mode 100644
index 0000000..ebf55d5
--- /dev/null
+++ b/usrp2/fpga/vrt/vita_rx_framer.v
@@ -0,0 +1,195 @@
+
+module vita_rx_framer
+ #(parameter BASE=0,
+ parameter MAXCHAN=1)
+ (input clk, input reset, input clear,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ // To FIFO interface of Buffer Pool
+ output [35:0] data_o,
+ input dst_rdy_i,
+ output src_rdy_o,
+
+ // From vita_rx_control
+ input [4+64+(32*MAXCHAN)-1:0] sample_fifo_i,
+ input sample_fifo_src_rdy_i,
+ output sample_fifo_dst_rdy_o,
+
+ // FIFO Levels
+ output [15:0] fifo_occupied,
+ output fifo_full,
+ output fifo_empty,
+
+ output [31:0] debug_rx
+ );
+
+ localparam SAMP_WIDTH = 4+64+(32*MAXCHAN);
+ reg [3:0] sample_phase;
+ wire [3:0] numchan;
+ wire [3:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-4];
+ wire [63:0] vita_time_fifo_o =
sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68];
+
+ reg [31:0] data_fifo_o;
+ wire [127:0] XILINX_SUCKS = sample_fifo_i;
+ always @*
+ case(sample_phase)
+ 4'd0 : data_fifo_o = XILINX_SUCKS[31:0];
+ 4'd1 : data_fifo_o = XILINX_SUCKS[63:32];
+ 4'd2 : data_fifo_o = XILINX_SUCKS[95:64];
+ 4'd3 : data_fifo_o = XILINX_SUCKS[127:96];
+ default : data_fifo_o = 32'hDEADBEEF;
+ endcase // case (sample_phase)
+
+ wire clear_pkt_count, pkt_fifo_rdy, sample_fifo_in_rdy;
+
+ wire [31:0] vita_header, vita_streamid, vita_trailer;
+ wire [15:0] samples_per_packet;
+
+ reg [33:0] pkt_fifo_line;
+ reg [3:0] vita_state;
+ reg [15:0] sample_ctr;
+ reg [3:0] pkt_count;
+
+ wire [15:0] vita_pkt_len = samples_per_packet + 6;
+ //wire [3:0] flags =
{signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+
+ wire clear_reg;
+ wire clear_int = clear | clear_reg;
+
+ setting_reg #(.my_addr(BASE+3)) sr_clear
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(),.changed(clear_reg));
+
+ setting_reg #(.my_addr(BASE+4)) sr_header
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(vita_header),.changed());
+
+ setting_reg #(.my_addr(BASE+5)) sr_streamid
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(vita_streamid),.changed(clear_pkt_count));
+
+ setting_reg #(.my_addr(BASE+6)) sr_trailer
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(vita_trailer),.changed());
+
+ setting_reg #(.my_addr(BASE+7)) sr_samples_per_pkt
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(samples_per_packet),.changed());
+
+ setting_reg #(.my_addr(BASE+8), .at_reset(1)) sr_numchan
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(numchan),.changed());
+
+ // Output FIFO for packetized data
+ localparam VITA_IDLE = 0;
+ localparam VITA_HEADER = 1;
+ localparam VITA_STREAMID = 2;
+ localparam VITA_SECS = 3;
+ localparam VITA_TICS = 4;
+ localparam VITA_TICS2 = 5;
+ localparam VITA_PAYLOAD = 6;
+ localparam VITA_TRAILER = 7;
+ localparam VITA_ERR_HEADER = 9; // All ERR at 4'b1000 or'ed with base
+ localparam VITA_ERR_STREAMID = 10;
+ localparam VITA_ERR_SECS = 11;
+ localparam VITA_ERR_TICS = 12;
+ localparam VITA_ERR_TICS2 = 13;
+ localparam VITA_ERR_PAYLOAD = 14;
+ localparam VITA_ERR_TRAILER = 15;
+
+ always @(posedge clk)
+ if(reset | clear_pkt_count)
+ pkt_count <= 0;
+ else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy)
+ pkt_count <= pkt_count + 1;
+
+ always @*
+ case(vita_state)
+ VITA_HEADER, VITA_ERR_HEADER : pkt_fifo_line <=
{2'b01,vita_header[31:20],pkt_count,vita_pkt_len};
+ VITA_STREAMID, VITA_ERR_STREAMID : pkt_fifo_line <=
{2'b00,vita_streamid};
+ VITA_SECS, VITA_ERR_SECS : pkt_fifo_line <=
{2'b00,vita_time_fifo_o[63:32]};
+ VITA_TICS, VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
+ VITA_TICS2, VITA_ERR_TICS2 : pkt_fifo_line <=
{2'b00,vita_time_fifo_o[31:0]};
+ VITA_PAYLOAD : pkt_fifo_line <= {2'b00,data_fifo_o};
+ VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b00,28'd0,flags_fifo_o};
+ VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer};
+ VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
+ default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
+ endcase // case (vita_state)
+
+ always @(posedge clk)
+ if(reset)
+ begin
+ vita_state <= VITA_IDLE;
+ sample_ctr <= 0;
+ sample_phase <= 0;
+ end
+ else
+ if(vita_state==VITA_IDLE)
+ begin
+ sample_ctr <= 1;
+ sample_phase <= 0;
+ if(sample_fifo_src_rdy_i)
+ if(|flags_fifo_o[3:1])
+ vita_state <= VITA_ERR_HEADER;
+ else
+ vita_state <= VITA_HEADER;
+ end
+ else if(pkt_fifo_rdy)
+ case(vita_state)
+ VITA_PAYLOAD :
+ if(sample_fifo_src_rdy_i)
+ begin
+ if(sample_phase == (numchan-4'd1))
+ begin
+ sample_phase <= 0;
+ sample_ctr <= sample_ctr + 1;
+ if(sample_ctr == samples_per_packet)
+ vita_state <= VITA_TRAILER;
+ if(|flags_fifo_o) // end early if any flag is set
+ vita_state <= VITA_TRAILER;
+ end
+ else
+ sample_phase <= sample_phase + 1;
+ end
+ VITA_TRAILER, VITA_ERR_TRAILER :
+ vita_state <= VITA_IDLE;
+ default :
+ vita_state <= vita_state + 1;
+ endcase // case (vita_state)
+
+ reg req_write_pkt_fifo;
+ always @*
+ case(vita_state)
+ VITA_IDLE :
+ req_write_pkt_fifo <= 0;
+ VITA_HEADER, VITA_STREAMID, VITA_SECS, VITA_TICS, VITA_TICS2,
VITA_TRAILER :
+ req_write_pkt_fifo <= 1;
+ VITA_PAYLOAD :
+ // Write if sample ready and no error flags
+ req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
+ VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS,
VITA_ERR_TICS2, VITA_ERR_PAYLOAD, VITA_ERR_TRAILER :
+ req_write_pkt_fifo <= 1;
+ default :
+ req_write_pkt_fifo <= 0;
+ endcase // case (vita_state)
+
+ //wire req_write_pkt_fifo = (vita_state != VITA_IDLE) &
(sample_fifo_src_rdy_i | (vita_state != VITA_PAYLOAD));
+
+ // Short FIFO to buffer between us and the FIFOs outside
+ fifo_short #(.WIDTH(34)) rx_pkt_fifo
+ (.clk(clk), .reset(reset), .clear(clear_int),
+ .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo),
.dst_rdy_o(pkt_fifo_rdy),
+ .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+ .space(),.occupied(fifo_occupied[4:0]) );
+ assign fifo_occupied[15:5] = 0;
+ assign data_o[35:34] = 2'b00; // Always write full lines
+ assign sample_fifo_dst_rdy_o = pkt_fifo_rdy &
+ ( ((vita_state==VITA_PAYLOAD) &
+ (sample_phase == (numchan-4'd1)) &
+ ~|flags_fifo_o[3:1]) |
+ (vita_state==VITA_ERR_TRAILER));
+
+ assign debug_rx = 0;
+
+endmodule // rx_control
diff --git a/usrp2/fpga/vrt/vita_rx_tb.v b/usrp2/fpga/vrt/vita_rx_tb.v
new file mode 100644
index 0000000..bc62c68
--- /dev/null
+++ b/usrp2/fpga/vrt/vita_rx_tb.v
@@ -0,0 +1,211 @@
+
+
+module vita_rx_tb;
+
+ localparam DECIM = 8'd4;
+ localparam MAXCHAN=4;
+ localparam NUMCHAN=4;
+
+ reg clk = 0;
+ reg reset = 1;
+
+ initial #1000 reset = 0;
+ always #50 clk = ~clk;
+
+ initial $dumpfile("vita_rx_tb.vcd");
+ initial $dumpvars(0,vita_rx_tb);
+
+ wire [(MAXCHAN*32)-1:0] sample;
+ wire strobe, run;
+ wire [35:0] data_o;
+ wire src_rdy;
+ reg dst_rdy = 1;
+ wire [63:0] vita_time;
+
+ reg set_stb = 0;
+ reg [7:0] set_addr;
+ reg [31:0] set_data;
+ wire set_stb_dsp;
+ wire [7:0] set_addr_dsp;
+ wire [31:0] set_data_dsp;
+
+ settings_bus_crossclock settings_bus_xclk_dsp
+ (.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr),
.set_data_i(set_data),
+ .clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp),
.set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
+
+ wire sample_dst_rdy, sample_src_rdy;
+ //wire [99:0] sample_data_o;
+ wire [64+4+(MAXCHAN*32)-1:0] sample_data_o;
+
+ vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
+ (.clk(clk), .reset(reset), .clear(0),
+ .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+ .vita_time(vita_time), .overrun(overrun),
+ .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy),
.sample_fifo_src_rdy_o(sample_src_rdy),
+ .sample(sample), .run(run), .strobe(strobe));
+
+ vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer
+ (.clk(clk), .reset(reset), .clear(0),
+ .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+ .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy),
+ .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy),
.sample_fifo_src_rdy_i(sample_src_rdy),
+ .fifo_occupied(), .fifo_full(), .fifo_empty() );
+
+ rx_dsp_model rx_dsp_model
+ (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe),
.sample(sample[31:0]));
+
+ generate
+ if(MAXCHAN>1)
+ assign sample[(MAXCHAN*32)-1:32] = 0;
+ endgenerate
+
+ time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit
+ (.clk(clk), .rst(reset),
+ .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+ .pps(0), .vita_time(vita_time));
+
+ always @(posedge clk)
+ if(src_rdy & dst_rdy)
+ begin
+ if(data_o[32] & ~data_o[33])
+ begin
+ $display("RX-PKT-START %d",$time);
+ $display(" RX-PKT-DAT %x",data_o[31:0]);
+ end
+ else if(data_o[32] & data_o[33])
+ begin
+ $display(" RX-PKT-DAT %x -- With ERR",data_o[31:0]);
+ $display("RX-PKT-ERR %d",$time);
+ end
+ else if(~data_o[32] & data_o[33])
+ begin
+ $display(" RX-PKT-DAT %x",data_o[31:0]);
+ $display("RX-PKT-END %d",$time);
+ end
+ else
+ $display(" RX-PKT DAT %x",data_o[31:0]);
+ end
+
+ initial
+ begin
+ @(negedge reset);
+ @(posedge clk);
+ write_setting(4,32'hDEADBEEF); // VITA header
+ write_setting(5,32'hF00D1234); // VITA streamid
+ write_setting(6,32'h98765432); // VITA trailer
+ write_setting(7,8); // Samples per VITA packet
+ write_setting(8,NUMCHAN); // Samples per VITA packet
+ queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet
+ queue_rx_cmd(1,0,16,32'h0,32'h0); // send imm, 2 packets worth
+ queue_rx_cmd(1,0,7,32'h0,32'h0); // send imm, 1 short packet worth
+ queue_rx_cmd(1,0,9,32'h0,32'h0); // send imm, just longer than 1 packet
+
+ queue_rx_cmd(1,1,16,32'h0,32'h0); // chained
+ queue_rx_cmd(0,0,8,32'h0,32'h0); // 2nd in chain
+
+ queue_rx_cmd(1,1,17,32'h0,32'h0); // chained, odd length
+ queue_rx_cmd(0,0,9,32'h0,32'h0); // 2nd in chain, also odd length
+
+ queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time
+ queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late
+
+ queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain
+ #100000;
+ $display("\nEnd chain with zero samples, shouldn't error\n");
+ queue_rx_cmd(1,1,8,32'h0,32'h0); // chained
+ queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples,
should keep us out of error
+ #100000;
+
+ $display("\nEnd chain with zero samples on odd-length, shouldn't
error\n");
+ queue_rx_cmd(1,1,14,32'h0,32'h0); // chained
+ queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples,
should keep us out of error
+ #100000;
+ $display("Should have gotten 14 samples and EOF by now\n");
+
+ queue_rx_cmd(1,1,9,32'h0,32'h0); // chained, but break chain, odd
length
+ #100000;
+ dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun
+ queue_rx_cmd(1,0,100,32'h0,32'h0); // long enough to fill the fifos
+ queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the
previous error packet is sent
+ #100000;
+ dst_rdy <= 1; // restart the reads so we can see what we got
+ #100000;
+ dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun
+ queue_rx_cmd(1,1,100,32'h0,32'h0); // long enough to fill the fifos
+ //queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the
previous error packet is sent
+ #100000;
+ @(posedge clk);
+ dst_rdy <= 1;
+
+ #100000 $finish;
+ end
+
+ task write_setting;
+ input [7:0] addr;
+ input [31:0] data;
+ begin
+ set_stb <= 0;
+ @(posedge clk);
+ set_addr <= addr;
+ set_data <= data;
+ set_stb <= 1;
+ @(posedge clk);
+ set_stb <= 0;
+ end
+ endtask // write_setting
+
+ task queue_rx_cmd;
+ input send_imm;
+ input chain;
+ input [29:0] lines;
+ input [31:0] secs;
+ input [31:0] tics;
+ begin
+ write_setting(0,{send_imm,chain,lines});
+ write_setting(1,secs);
+ write_setting(2,tics);
+ end
+ endtask // queue_rx_cmd
+
+endmodule // rx_control_tb
+
+module rx_dsp_model
+ (input clk, input reset,
+ input run,
+ input [7:0] decim,
+ output strobe,
+ output [31:0] sample);
+
+ reg [15:0] pktnum = 0;
+ reg [15:0] counter = 0;
+
+ reg run_d1;
+ always @(posedge clk) run_d1 <= run;
+
+ always @(posedge clk)
+ if(run & ~run_d1)
+ begin
+ counter <= 0;
+ pktnum <= pktnum + 1;
+ end
+ else if(run & strobe)
+ counter <= counter + 1;
+
+ assign sample = {pktnum,counter};
+
+ reg [7:0] stb_ctr = 0;
+
+ always @(posedge clk)
+ if(reset)
+ stb_ctr <= 0;
+ else if(run & ~run_d1)
+ stb_ctr <= 1;
+ else if(run)
+ if(stb_ctr == decim-1)
+ stb_ctr <= 0;
+ else
+ stb_ctr <= stb_ctr + 1;
+
+ assign strobe = stb_ctr == decim-1;
+
+endmodule // rx_dsp_model
diff --git a/usrp2/fpga/vrt/vita_tx_control.v b/usrp2/fpga/vrt/vita_tx_control.v
new file mode 100644
index 0000000..2e96e6d
--- /dev/null
+++ b/usrp2/fpga/vrt/vita_tx_control.v
@@ -0,0 +1,174 @@
+
+module vita_rx_control
+ #(parameter BASE=0,
+ parameter WIDTH=32)
+ (input clk, input reset, input clear,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ input [63:0] vita_time,
+ output overrun,
+
+ // To vita_rx_framer
+ output [4+64+WIDTH-1:0] sample_fifo_o,
+ output sample_fifo_src_rdy_o,
+ input sample_fifo_dst_rdy_i,
+
+ // From DSP Core
+ input [WIDTH-1:0] sample,
+ output run,
+ input strobe,
+
+ output [31:0] debug_rx
+ );
+
+ // FIXME add TX Interruption (halt, pause, continue) functionality
+
+ wire [63:0] new_time;
+ wire [31:0] new_command;
+ wire sc_pre1, clear_int, clear_reg;
+
+ assign clear_int = clear | clear_reg;
+
+ wire [63:0] rcvtime_pre;
+ reg [63:0] rcvtime;
+ wire [29:0] numlines_pre;
+ wire send_imm_pre, chain_pre;
+ reg send_imm, chain;
+ wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
+ reg sc_pre2;
+ wire [33:0] fifo_line;
+ reg [29:0] lines_left;
+ reg [2:0] ibs_state;
+ wire now, early, late;
+ wire sample_fifo_in_rdy;
+
+ setting_reg #(.my_addr(BASE)) sr_cmd
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(new_command),.changed());
+
+ setting_reg #(.my_addr(BASE+1)) sr_time_h
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(new_time[63:32]),.changed());
+
+ setting_reg #(.my_addr(BASE+2)) sr_time_l
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(new_time[31:0]),.changed(sc_pre1));
+
+ setting_reg #(.my_addr(BASE+3)) sr_clear
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(),.changed(clear_reg));
+
+ // FIFO to store commands sent from the settings bus
+ always @(posedge clk)
+ sc_pre2 <= sc_pre1;
+ assign write_ctrl = sc_pre1 & ~sc_pre2;
+
+ wire [4:0] command_queue_len;
+ shortfifo #(.WIDTH(96)) commandfifo
+ (.clk(clk),.rst(reset),.clear(clear_int),
+ .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl),
.full(full_ctrl),
+ .dataout({send_imm_pre,chain_pre,numlines_pre,rcvtime_pre}),
+ .read(read_ctrl), .empty(empty_ctrl),
+ .occupied(command_queue_len), .space() );
+
+ reg [33:0] pkt_fifo_line;
+
+ localparam IBS_IDLE = 0;
+ localparam IBS_WAITING = 1;
+ localparam IBS_RUNNING = 2;
+ localparam IBS_OVERRUN = 4;
+ localparam IBS_BROKENCHAIN = 5;
+ localparam IBS_LATECMD = 6;
+
+ wire signal_cmd_done = (lines_left == 1) & (~chain | (~empty_ctrl &
(numlines_pre==0)));
+ wire signal_overrun = (ibs_state == IBS_OVERRUN);
+ wire signal_brokenchain = (ibs_state == IBS_BROKENCHAIN);
+ wire signal_latecmd = (ibs_state == IBS_LATECMD);
+
+ // Buffer of samples for while we're writing the packet headers
+ wire [3:0] flags =
{signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+
+ wire attempt_sample_write = ((run & strobe) |
(ibs_state==IBS_OVERRUN) |
+ (ibs_state==IBS_BROKENCHAIN) |
(ibs_state==IBS_LATECMD));
+
+ fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo
+ (.clk(clk),.reset(reset),.clear(clear_int),
+ .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write),
.dst_rdy_o(sample_fifo_in_rdy),
+ .dataout(sample_fifo_o),
+ .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i),
+ .space(), .occupied() );
+
+ // Inband Signalling State Machine
+ time_compare
+ time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now),
.early(early), .late(late));
+
+ wire too_late = late & ~send_imm;
+ wire go_now = now | send_imm;
+ wire full = ~sample_fifo_in_rdy;
+
+ always @(posedge clk)
+ if(reset | clear_int)
+ begin
+ ibs_state <= IBS_IDLE;
+ lines_left <= 0;
+ rcvtime <= 0;
+ send_imm <= 0;
+ chain <= 0;
+ end
+ else
+ case(ibs_state)
+ IBS_IDLE :
+ if(~empty_ctrl)
+ begin
+ lines_left <= numlines_pre;
+ rcvtime <= rcvtime_pre;
+ ibs_state <= IBS_WAITING;
+ send_imm <= send_imm_pre;
+ chain <= chain_pre;
+ end
+ IBS_WAITING :
+ if(go_now)
+ ibs_state <= IBS_RUNNING;
+ else if(too_late)
+ ibs_state <= IBS_LATECMD;
+ IBS_RUNNING :
+ if(strobe)
+ if(full)
+ ibs_state <= IBS_OVERRUN;
+ else
+ begin
+ lines_left <= lines_left - 1;
+ if(lines_left == 1)
+ if(~chain)
+ ibs_state <= IBS_IDLE;
+ else if(empty_ctrl)
+ ibs_state <= IBS_BROKENCHAIN;
+ else
+ begin
+ lines_left <= numlines_pre;
+ rcvtime <= rcvtime_pre;
+ send_imm <= send_imm_pre;
+ chain <= chain_pre;
+ if(numlines_pre == 0) // If we are told to stop here
+ ibs_state <= IBS_IDLE;
+ else
+ ibs_state <= IBS_RUNNING;
+ end
+ end // else: !if(full)
+ IBS_OVERRUN, IBS_LATECMD, IBS_BROKENCHAIN :
+ if(sample_fifo_in_rdy)
+ ibs_state <= IBS_IDLE;
+ endcase // case(ibs_state)
+
+ assign overrun = (ibs_state == IBS_OVERRUN);
+ assign run = (ibs_state == IBS_RUNNING);
+
+ assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING)
& strobe & ~full & (lines_left==1) & chain) )
+ & ~empty_ctrl;
+
+ assign debug_rx = { { ibs_state[2:0], command_queue_len },
+ { 8'd0 },
+ { go_now, too_late, run, strobe, read_ctrl, write_ctrl,
full_ctrl, empty_ctrl },
+ { 2'b0, overrun, chain_pre, sample_fifo_in_rdy,
attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
+
+endmodule // rx_control
diff --git a/usrp2/fpga/vrt/vita_tx_deframer.v
b/usrp2/fpga/vrt/vita_tx_deframer.v
new file mode 100644
index 0000000..4a3430b
--- /dev/null
+++ b/usrp2/fpga/vrt/vita_tx_deframer.v
@@ -0,0 +1,269 @@
+
+module vita_tx_deframer
+ #(parameter BASE=0,
+ parameter MAXCHAN=1)
+ (input clk, input reset, input clear,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ // To FIFO interface of Buffer Pool
+ input [35:0] data_i,
+ input src_rdy_i,
+ output dst_rdy_o,
+
+ output [4+64+(32*MAXCHAN)-1:0] sample_fifo_o,
+ output sample_fifo_src_rdy_o,
+ input sample_fifo_dst_rdy_i,
+
+ // FIFO Levels
+ output [15:0] fifo_occupied,
+ output fifo_full,
+ output fifo_empty
+ );
+
+
+ reg [3:0] vita_state;
+ wire has_streamid, has_classid, has_secs, has_tics, has_trailer;
+ assign has_streamid = (data_i[31:28]==4'b001);
+ assign has_classid = data_i[27];
+ assign has_secs = ~(data[23:22]==2'b00);
+ assign has_tics = ~(data[21:20]==2'b00);
+ assign has_trailer = data[26];
+
+
+ reg has_streamid_reg, has_classid_reg, has_secs_reg,
has_tics_reg, has_trailer_reg;
+ // Output FIFO for packetized data
+ localparam VITA_HEADER = 0;
+ localparam VITA_STREAMID = 1;
+ localparam VITA_CLASSID = 2;
+ localparam VITA_CLASSID2 = 3;
+ localparam VITA_SECS = 4;
+ localparam VITA_TICS = 5;
+ localparam VITA_TICS2 = 6;
+ localparam VITA_PAYLOAD = 7;
+ localparam VITA_TRAILER = 8;
+ localparam VITA_ERR_HEADER = 9; // All ERR at 4'b1000 or'ed with base
+ localparam VITA_ERR_STREAMID = 10;
+ localparam VITA_ERR_SECS = 11;
+ localparam VITA_ERR_TICS = 12;
+ localparam VITA_ERR_TICS2 = 13;
+ localparam VITA_ERR_PAYLOAD = 14;
+ localparam VITA_ERR_TRAILER = 15;
+
+
+ always @(posedge clk)
+ if(reset | clear)
+ begin
+ vita_state <= VITA_HEADER;
+ {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg,
has_trailer_reg}
+ <= 0;
+ else if(src_rdy_i & sample_fifo_dst_rdy_i)
+ case(vita_state)
+ VITA_HEADER :
+ begin
+ {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg,
has_trailer_reg}
+ <= {has_streamid, has_classid, has_secs, has_tics, has_trailer};
+ if(has_streamid)
+ vita_state <= VITA_STREAMID;
+ else if(has_classid)
+ vita_state <= VITA_CLASSID;
+ else if(has_secs)
+ vita_state <= VITA_SECS;
+ else if(has_tics)
+ vita_state <= VITA_TICS;
+ else
+ vita_state <= VITA_PAYLOAD;
+ end // case: VITA_HEADER
+ VITA_STREAMID :
+ if(has_classid_reg)
+ vita_state <= VITA_CLASSID;
+ else if(has_secs_reg)
+ vita_state <= VITA_SECS;
+ else if(has_tics_reg)
+ vita_state <= VITA_TICS;
+ else
+ vita_state <= VITA_PAYLOAD;
+ VITA_CLASSID :
+ vita_state <= VITA_CLASSID2;
+ VITA_CLASSID2 :
+ if(has_secs_reg)
+ vita_state <= VITA_SECS;
+ else if(has_tics_reg)
+ vita_state <= VITA_TICS;
+ else
+ vita_state <= VITA_PAYLOAD;
+ VITA_SECS :
+ else if(has_tics_reg)
+ vita_state <= VITA_TICS;
+ else
+ vita_state <= VITA_PAYLOAD;
+ VITA_TICS :
+ vita_state <= VITA_TICS2;
+ VITA_TICS2 :
+ vita_state <= VITA_PAYLOAD;
+ VITA_PAYLOAD :
+ if(has_trailer_reg)
+ vita_state <= VITA_TRAILER;
+ else
+ vita_state <= VITA_HEADER;
+ VITA_TRAILER :
+ vita_state <= VITA_HEADER;
+ endcase // case (vita_state)
+
+
+ always @*
+ case(vita_state)
+ VITA_HEADER, VITA_ERR_HEADER : pkt_fifo_line <=
{2'b01,vita_header[31:20],pkt_count,vita_pkt_len};
+ VITA_STREAMID, VITA_ERR_STREAMID : pkt_fifo_line <=
{2'b00,vita_streamid};
+ VITA_SECS, VITA_ERR_SECS : pkt_fifo_line <=
{2'b00,vita_time_fifo_o[63:32]};
+ VITA_TICS, VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
+ VITA_TICS2, VITA_ERR_TICS2 : pkt_fifo_line <=
{2'b00,vita_time_fifo_o[31:0]};
+ VITA_PAYLOAD : pkt_fifo_line <= {2'b00,data_fifo_o};
+ VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b00,28'd0,flags_fifo_o};
+ VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer};
+ VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
+ default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
+ endcase // case (vita_state)
+
+
+
+
+
+ localparam SAMP_WIDTH = 4+64+(32*MAXCHAN);
+ reg [3:0] sample_phase;
+ wire [3:0] numchan;
+ wire [3:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-4];
+ wire [63:0] vita_time_fifo_o =
sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68];
+
+ reg [31:0] data_fifo_o;
+ wire [127:0] XILINX_SUCKS = sample_fifo_i;
+ always @*
+ case(sample_phase)
+ 4'd0 : data_fifo_o = XILINX_SUCKS[31:0];
+ 4'd1 : data_fifo_o = XILINX_SUCKS[63:32];
+ 4'd2 : data_fifo_o = XILINX_SUCKS[95:64];
+ 4'd3 : data_fifo_o = XILINX_SUCKS[127:96];
+ default : data_fifo_o = 32'hDEADBEEF;
+ endcase // case (sample_phase)
+
+ wire clear_pkt_count, pkt_fifo_rdy, sample_fifo_in_rdy;
+
+ wire [31:0] vita_header, vita_streamid, vita_trailer;
+ wire [15:0] samples_per_packet;
+
+ reg [33:0] pkt_fifo_line;
+ reg [3:0] vita_state;
+ reg [15:0] sample_ctr;
+ reg [3:0] pkt_count;
+
+ wire [15:0] vita_pkt_len = samples_per_packet + 6;
+ //wire [3:0] flags =
{signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+
+ wire clear_reg;
+ wire clear_int = clear | clear_reg;
+
+ setting_reg #(.my_addr(BASE+3)) sr_clear
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(),.changed(clear_reg));
+
+ setting_reg #(.my_addr(BASE+4)) sr_header
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(vita_header),.changed());
+
+ setting_reg #(.my_addr(BASE+5)) sr_streamid
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(vita_streamid),.changed(clear_pkt_count));
+
+ setting_reg #(.my_addr(BASE+6)) sr_trailer
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(vita_trailer),.changed());
+
+ setting_reg #(.my_addr(BASE+7)) sr_samples_per_pkt
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(samples_per_packet),.changed());
+
+ setting_reg #(.my_addr(BASE+8), .at_reset(1)) sr_numchan
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(numchan),.changed());
+
+ always @(posedge clk)
+ if(reset | clear_pkt_count)
+ pkt_count <= 0;
+ else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy)
+ pkt_count <= pkt_count + 1;
+
+ always @(posedge clk)
+ if(reset)
+ begin
+ vita_state <= VITA_IDLE;
+ sample_ctr <= 0;
+ sample_phase <= 0;
+ end
+ else
+ if(vita_state==VITA_IDLE)
+ begin
+ sample_ctr <= 1;
+ sample_phase <= 0;
+ if(sample_fifo_src_rdy_i)
+ if(|flags_fifo_o[3:1])
+ vita_state <= VITA_ERR_HEADER;
+ else
+ vita_state <= VITA_HEADER;
+ end
+ else if(pkt_fifo_rdy)
+ case(vita_state)
+ VITA_PAYLOAD :
+ if(sample_fifo_src_rdy_i)
+ begin
+ if(sample_phase == (numchan-4'd1))
+ begin
+ sample_phase <= 0;
+ sample_ctr <= sample_ctr + 1;
+ if(sample_ctr == samples_per_packet)
+ vita_state <= VITA_TRAILER;
+ if(|flags_fifo_o) // end early if any flag is set
+ vita_state <= VITA_TRAILER;
+ end
+ else
+ sample_phase <= sample_phase + 1;
+ end
+ VITA_TRAILER, VITA_ERR_TRAILER :
+ vita_state <= VITA_IDLE;
+ default :
+ vita_state <= vita_state + 1;
+ endcase // case (vita_state)
+
+ reg req_write_pkt_fifo;
+ always @*
+ case(vita_state)
+ VITA_IDLE :
+ req_write_pkt_fifo <= 0;
+ VITA_HEADER, VITA_STREAMID, VITA_SECS, VITA_TICS, VITA_TICS2,
VITA_TRAILER :
+ req_write_pkt_fifo <= 1;
+ VITA_PAYLOAD :
+ // Write if sample ready and no error flags
+ req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
+ VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS,
VITA_ERR_TICS2, VITA_ERR_PAYLOAD, VITA_ERR_TRAILER :
+ req_write_pkt_fifo <= 1;
+ default :
+ req_write_pkt_fifo <= 0;
+ endcase // case (vita_state)
+
+ //wire req_write_pkt_fifo = (vita_state != VITA_IDLE) &
(sample_fifo_src_rdy_i | (vita_state != VITA_PAYLOAD));
+
+ // Short FIFO to buffer between us and the FIFOs outside
+ fifo_short #(.WIDTH(34)) rx_pkt_fifo
+ (.clk(clk), .reset(reset), .clear(clear_int),
+ .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo),
.dst_rdy_o(pkt_fifo_rdy),
+ .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+ .space(),.occupied(fifo_occupied[4:0]) );
+ assign fifo_occupied[15:5] = 0;
+ assign data_o[35:34] = 2'b00; // Always write full lines
+ assign sample_fifo_dst_rdy_o = pkt_fifo_rdy &
+ ( ((vita_state==VITA_PAYLOAD) &
+ (sample_phase == (numchan-4'd1)) &
+ ~|flags_fifo_o[3:1]) |
+ (vita_state==VITA_ERR_TRAILER));
+
+ assign debug_rx = 0;
+
+endmodule // rx_control
- [Commit-gnuradio] [gnuradio] 16/148: Put ethernet control transport into its own cc/h files. Ethernet control transport is in-charge of ethernet and transport headers, so that usrp2 impl knows nothing about ethernet stuff (as far as control goes)., (continued)
- [Commit-gnuradio] [gnuradio] 16/148: Put ethernet control transport into its own cc/h files. Ethernet control transport is in-charge of ethernet and transport headers, so that usrp2 impl knows nothing about ethernet stuff (as far as control goes)., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 24/148: vita rx instead of rx_control. Ready for firmware testing. Misses timing by a little bit, will worry later., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 33/148: got firmware compiling with vrt rx, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 34/148: forgot to declare wires, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 39/148: mostly just copied over from the rx side. Still needs a lot of work., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 40/148: Added missing flag to vrt header in txrx.c. Added parsing to vrt expanded header to copy out header entries. Modified usrp2 impl to use the correctly parsed header., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 35/148: got vrt rx somewhat working, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 52/148: seems to correctly deframe packets. now need to consume them., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 50/148: make the testbench work in this environment, without the crossclock settings bus, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 26/148: moved regs around for vita49, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 19/148: VITA49 rx (and tx skeleton) copied over from quad radio,
git <=
- [Commit-gnuradio] [gnuradio] 43/148: minor tweak to transport loop and debug printf for vrt, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 44/148: Removed temporary u2_eth_packet_only_t. Removed the fixed header portion from the u2_eth_packet_t. Removed places in code where control uses the fixed header (always unused 0 for word, and -1 for timestamp). Flagged the fixed header stuff for removal (once we get vrt tx)., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 25/148: cleanup, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 42/148: Created a ring data structure held by the ring. It holds an sbuff and its parsed vrt data (header, payload, and len). The impl data handler parses the packets and enqueues them., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 48/148: Added interrupt call from transport::stop so the recv or callback will throw at interruption points. This fixes the issue where the app would hang in the stop method when exiting (we were hanging here: d_data_pending_cond.wait(l), but now wait throws() and we exit)., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 54/148: flag packets which arrive way too early so the device doesn't sit there forever., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 38/148: rx working with vrt header, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 45/148: Re-implemented find.cc with gruel and eth_ctrl_transport class. Added constructor args to the eth control transport to set the timeout and target for the packet filter., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 49/148: Added read_packet with timeout method to ethernet. Now the control recv can timeout and immediately recv., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 21/148: put 64 bit timer for vita49 on the settings bus, git, 2016/08/14