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[Commit-gnuradio] [gnuradio] 26/148: moved regs around for vita49
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git |
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[Commit-gnuradio] [gnuradio] 26/148: moved regs around for vita49 |
Date: |
Mon, 15 Aug 2016 00:47:21 +0000 (UTC) |
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nwest pushed a commit to annotated tag old_usrp_devel_udp
in repository gnuradio.
commit 7b0fcf9d0458c3264db3dbfd5d9d181c2ce648c3
Author: Matt Ettus <address@hidden>
Date: Thu Nov 5 17:31:39 2009 -0800
moved regs around for vita49
---
usrp2/fpga/sdr_lib/dsp_core_rx.v | 16 ++++++++--------
usrp2/fpga/top/u2_core/u2_core.v | 9 +++++----
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/usrp2/fpga/sdr_lib/dsp_core_rx.v b/usrp2/fpga/sdr_lib/dsp_core_rx.v
index af4f0b9..2ac4296 100644
--- a/usrp2/fpga/sdr_lib/dsp_core_rx.v
+++ b/usrp2/fpga/sdr_lib/dsp_core_rx.v
@@ -1,6 +1,6 @@
-`define DSP_CORE_RX_BASE 160
module dsp_core_rx
+ #(parameter BASE = 160)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -33,33 +33,33 @@ module dsp_core_rx
wire enable_hb1, enable_hb2;
wire [7:0] cic_decim_rate;
- setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
+ setting_reg #(.my_addr(BASE+0)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_inc),.changed());
- setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
+ setting_reg #(.my_addr(BASE+1)) sr_1
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({scale_i,scale_q}),.changed());
- setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
+ setting_reg #(.my_addr(BASE+2)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
- rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
+ rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_in(adc_a),.adc_out(adc_a_ofs));
- rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
+ rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_in(adc_b),.adc_out(adc_b_ofs));
wire [3:0] muxctrl;
- setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8
+ setting_reg #(.my_addr(BASE+5)) sr_8
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(muxctrl),.changed());
wire [1:0] gpio_ena;
- setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9
+ setting_reg #(.my_addr(BASE+6)) sr_9
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(gpio_ena),.changed());
diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v
index 48440e2..ea4451c 100644
--- a/usrp2/fpga/top/u2_core/u2_core.v
+++ b/usrp2/fpga/top/u2_core/u2_core.v
@@ -136,7 +136,8 @@ module u2_core
input [3:0] clock_divider
);
- localparam SR_RXCTRL = 160;
+ localparam SR_RX_DSP = 160;
+ localparam SR_RX_CTRL = 176;
localparam SR_TIME64 = 192;
wire [7:0] set_addr;
@@ -565,14 +566,14 @@ module u2_core
.fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
.debug_rx(debug_rx) );
*/
- vita_rx_control #(.BASE(SR_RXCTRL)) vita_rx_control
+ vita_rx_control #(.BASE(SR_RX_CTRL)) vita_rx_control
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.vita_time(vita_time), .overrun(overrun),
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
.sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy),
.sample_fifo_src_rdy_o(rx_src_rdy));
- vita_rx_framer #(.BASE(SR_RXCTRL)) vita_rx_framer
+ vita_rx_framer #(.BASE(SR_RX_CTRL)) vita_rx_framer
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy),
.sample_fifo_src_rdy_i(rx_src_rdy),
@@ -584,7 +585,7 @@ module u2_core
.datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
.dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i),
.dst_rdy_i(wr1_ready_o));
- dsp_core_rx dsp_core_rx
+ dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
- [Commit-gnuradio] [gnuradio] 27/148: new memory map for vita49. Apps won't compile, since symbol names are different, (continued)
- [Commit-gnuradio] [gnuradio] 27/148: new memory map for vita49. Apps won't compile, since symbol names are different, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 16/148: Put ethernet control transport into its own cc/h files. Ethernet control transport is in-charge of ethernet and transport headers, so that usrp2 impl knows nothing about ethernet stuff (as far as control goes)., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 24/148: vita rx instead of rx_control. Ready for firmware testing. Misses timing by a little bit, will worry later., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 33/148: got firmware compiling with vrt rx, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 34/148: forgot to declare wires, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 39/148: mostly just copied over from the rx side. Still needs a lot of work., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 40/148: Added missing flag to vrt header in txrx.c. Added parsing to vrt expanded header to copy out header entries. Modified usrp2 impl to use the correctly parsed header., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 35/148: got vrt rx somewhat working, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 52/148: seems to correctly deframe packets. now need to consume them., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 50/148: make the testbench work in this environment, without the crossclock settings bus, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 26/148: moved regs around for vita49,
git <=
- [Commit-gnuradio] [gnuradio] 19/148: VITA49 rx (and tx skeleton) copied over from quad radio, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 43/148: minor tweak to transport loop and debug printf for vrt, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 44/148: Removed temporary u2_eth_packet_only_t. Removed the fixed header portion from the u2_eth_packet_t. Removed places in code where control uses the fixed header (always unused 0 for word, and -1 for timestamp). Flagged the fixed header stuff for removal (once we get vrt tx)., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 25/148: cleanup, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 42/148: Created a ring data structure held by the ring. It holds an sbuff and its parsed vrt data (header, payload, and len). The impl data handler parses the packets and enqueues them., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 48/148: Added interrupt call from transport::stop so the recv or callback will throw at interruption points. This fixes the issue where the app would hang in the stop method when exiting (we were hanging here: d_data_pending_cond.wait(l), but now wait throws() and we exit)., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 54/148: flag packets which arrive way too early so the device doesn't sit there forever., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 38/148: rx working with vrt header, git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 45/148: Re-implemented find.cc with gruel and eth_ctrl_transport class. Added constructor args to the eth control transport to set the timeout and target for the packet filter., git, 2016/08/14
- [Commit-gnuradio] [gnuradio] 49/148: Added read_packet with timeout method to ethernet. Now the control recv can timeout and immediately recv., git, 2016/08/14