Re: [Discuss-gnuradio] external clock

[Darrell Harmon]

Bdale Garbee wrote:

> Looking at options for locking all the clocks that are part of the EME
> station I'm building to my HP 58503A GPS-synced clock.  Searching the
> list archives, I found this note from Matt regarding the external clock
> input on the USRP:
>
> http://lists.gnu.org/archive/html/discuss-gnuradio/2005-03/msg00030.html
>
> Has anyone played with this?  
>
> Of particular interest is whether anyone has hacked the FPGA code to use
> the internal PLLs to retain a 64 Mhz sample clock using a 10 Mhz
> reference clock input to the board.
>
> Bdale
>
>
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>  
Maybe I can add something here as I have recently been trying to figure 
out how to do this with a board I have been designing.  I will have a 
BNC connector for 10MHz input and will be generating 3 clocks (80MHz, 
400MHz and 500MHz).

For the ADC clock I have been considering using a Crystek low phase 
noise VCXO that costs $41 and an ADF4001.  It is expensive, but it is 
the only way I have found yet to get sufficiently low phase noise at 
80MHz.  Nobody seems to stock 80MHz XTALs.  I believe for the DAC clock, 
I will be using a discrete LC VCO and an LMX2306 PLL.  Also in 
consideration is a SAW resonator.

I can't find any 64MHz VCXOs in any of my catalogs, but 64MHz crystals 
are definitely available.  I suspect that they are all 3rd overtone. 
Epson MA-506 64.0000M-C0 is in stock at Digikey and is 3rd overtone.  
Maybe some of us should work to design a VCXO around this part or 
something similar.  I believe the ADF4001 would work nicely for a PLL.  
I have a board with an ADF4001 on it and may order a crystal and see 
what I can get it to do.  I may consider going to a 64MHz ADC clock for 
my board to save the cost of the $41 VCXO.  The only problem I see is 
that the 3rd overtone XTAL may not have enough pullability.  
http://icmfg.com does custom crystals for $20 and it may be possible to 
get something more pullable that way (and also get my 80MHz clock).

You really don't want to clock an ADC with anything that has been 
through a FPGA.  The jitter (Phase noise) specs of the FPGA PLLs are 
horrible.  They are designed for clocking logic, and have really noisy 
power due to all the FPGA logic switching.  In the QFP package the FPGA 
"ground" can have 100s of mV of RF on it.

--
Darrell Harmon
100x100mm SBC running GNU/Linux:
http://dlharmon.com/sbc.html