[Help-gnucap] verilog-ams netlist loading

[John Griessen]

I am attempting to follow   
http://wiki.gnucap.org/dokuwiki/doku.php?id=gnucap:languages:verilog

I make a file with contents of the illustrated netlist and top level instances:



//amptest.net
paramset gp_npn npn;\
  .bf=150;\
endparamset
module amp (out in vcc);
  parameter rload=10k;
  resistor  #(.r(1M))   Rb1  (base, vcc);        // 1 megohm
  resistor  #(.r(100K)) Rb2  (base, 0  );
  resistor  #(100K)     Rc   (col,  vcc);
  resistor  #(.r(10K))  Re   (.p(emit), .n(0));
  capacitor #(.c(1m))   Ce   (.p(emit), .n(0));
  capacitor #(.c(1u))   Cin  (base, in );        // 1 millifarad
  gp_npn                Q1   (.c(col), .b(base), .e(emit));
  gp_npn                Q2   (.c(vcc), .b(col), .e(e2));
  resistor  #(.r(1K))   Re2  (e2,  0  );
  capacitor #(.c(10u))  Cout (e2,  out);
  resistor  #(.r(rload))Rload(out, 0 );
endmodule
amp      #(.rload(100K)) X1    (.out(out), .in(in), .vcc(vc));
vsource  #(.dc(15))      Vcc   (.p(vc), .n(0));
vsource  #(.ac(1))       Vin   (.p(in), .n(0));
resistor #(10K)          Rload (out, 0);

The I input it to gnucap 2008.12.03 RCS 26.105

--------------------------------------------------------
gnucap-verilog>get ./amptest.net
//amptest.net
paramset gp_npn npn;   .bf=150; endparamset
^ ? p: no match
  parameter rload=10k;
                     ^ ? syntax error
... (.r(1M))   Rb1  (base, vcc);        // 1 megohm
                                        ^ ? what's this?
... (.c(1u))   Cin  (base, in );        // 1 millifarad
                                        ^ ? what's this?
  gp_npn                Q1   (.c(col), .b(base), .e(emit));
  ^ ? gp_npn: no match
  gp_npn                Q2   (.c(vcc), .b(col), .e(e2));
  ^ ? gp_npn: no match
amp      #(.rload(100K)) X1    (.out(out), .in(in), .vcc(vc)
^ ? a: no match
vsource  #(.dc(15))      Vcc   (.p(vc), .n(0));
^ ? v: no match
vsource  #(.ac(1))       Vin   (.p(in), .n(0));
^ ? v: no match
resistor #(10K)          Rload (out, 0);
^ ? r: no match
gnucap-verilog>
---------------------------------------------------

How can I get past this with verilog mode?



John Griessen
--
Ecosensory   Austin TX