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Re: [Qemu-arm] [Qemu-devel] [PATCH v2 05/11] hw/intc/armv7m_nvic: Implem
From: |
Richard Henderson |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v2 05/11] hw/intc/armv7m_nvic: Implement cache ID registers |
Date: |
Fri, 9 Feb 2018 12:59:21 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/09/2018 08:58 AM, Peter Maydell wrote:
> M profile cores have a similar setup for cache ID registers
> to A profile:
> * Cache Level ID Register (CLIDR) is a fixed value
> * Cache Type Register (CTR) is a fixed value
> * Cache Size ID Registers (CCSIDR) are a bank of registers;
> which one you see is selected by the Cache Size Selection
> Register (CSSELR)
>
> The only difference is that they're in the NVIC memory mapped
> register space rather than being coprocessor registers.
> Implement the M profile view of them.
>
> Since neither Cortex-M3 nor Cortex-M4 implement caches,
> we don't need to update their init functions and can leave
> the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero.
> Newer cores (like the Cortex-M33) will want to be able to
> set these ID registers to non-zero values, though.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> v1->v2 changes: use FIELD() to define some constants;
> add compile-time assert that we won't index outside cssidr[]
> ---
> target/arm/cpu.h | 26 ++++++++++++++++++++++++++
> hw/intc/armv7m_nvic.c | 16 ++++++++++++++++
> target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 78 insertions(+)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-arm] [PATCH v2 00/11] v8m: minor missing regs and bugfixes, Peter Maydell, 2018/02/09
- [Qemu-arm] [PATCH v2 03/11] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops, Peter Maydell, 2018/02/09
- [Qemu-arm] [PATCH v2 04/11] hw/intc/armv7m_nvic: Implement v8M CPPWR register, Peter Maydell, 2018/02/09
- [Qemu-arm] [PATCH v2 02/11] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling, Peter Maydell, 2018/02/09
- [Qemu-arm] [PATCH v2 05/11] hw/intc/armv7m_nvic: Implement cache ID registers, Peter Maydell, 2018/02/09
- Re: [Qemu-arm] [Qemu-devel] [PATCH v2 05/11] hw/intc/armv7m_nvic: Implement cache ID registers,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 10/11] target/arm: Migrate v7m.other_sp, Peter Maydell, 2018/02/09
- [Qemu-arm] [PATCH v2 07/11] target/arm: Implement writing to CONTROL_NS for v8M, Peter Maydell, 2018/02/09
- [Qemu-arm] [PATCH v2 11/11] target/arm: Implement v8M MSPLIM and PSPLIM registers, Peter Maydell, 2018/02/09
- [Qemu-arm] [PATCH v2 09/11] target/arm: Add AIRCR to vmstate struct, Peter Maydell, 2018/02/09
- [Qemu-arm] [PATCH v2 08/11] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions, Peter Maydell, 2018/02/09
- [Qemu-arm] [PATCH v2 01/11] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC, Peter Maydell, 2018/02/09