[Qemu-devel] [PATCH 09/16] Peripheral driver for S3C SOC general purpose I/O

[Vincent Sanders]

Provides general purpose I/O handling, SOC identification registers
and external interrupt support

Signed-off-by: Vincent Sanders <address@hidden>
---
 Makefile.target   |    2 +-
 hw/s3c2410x.c     |   10 +++
 hw/s3c2440.c      |    9 ++
 hw/s3c24xx.h      |    7 ++
 hw/s3c24xx_gpio.c |  225 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 252 insertions(+), 1 deletions(-)
 create mode 100644 hw/s3c24xx_gpio.c

diff --git a/Makefile.target b/Makefile.target
index 2596943..52dcf4c 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -649,7 +649,7 @@ OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o 
tusb6010.o usb-musb.o
 OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
 OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o s3c24xx_timers.o
-OBJS+= s3c24xx_serial.o s3c24xx_rtc.o
+OBJS+= s3c24xx_serial.o s3c24xx_rtc.o s3c24xx_gpio.o
 OBJS+= s3c2410x.o s3c2440.o
 OBJS+= framebuffer.o
 OBJS+= syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
diff --git a/hw/s3c2410x.c b/hw/s3c2410x.c
index 21ecec2..c3b84a0 100644
--- a/hw/s3c2410x.c
+++ b/hw/s3c2410x.c
@@ -13,6 +13,10 @@
 
 #include "s3c2410x.h"
 
+/* S3C2410 SoC IDs */
+#define CPU_S3C2410X_IDENT_S3C2410X 0x32410000
+#define CPU_S3C2410X_IDENT_S3C2410A 0x32410002
+
 /* Integrated peripherals */
 
 /* SRAM */
@@ -36,6 +40,9 @@
 /* Timer controller */
 #define CPU_S3C2410X_TIMERS_BASE (CPU_S3C2410X_PERIPHERAL + 0x11000000)
 
+/* GPIO */
+#define CPU_S3C2410X_GPIO_BASE (CPU_S3C2410X_PERIPHERAL + 0x16000000)
+
 /* Real time clock */
 #define CPU_S3C2410X_RTC_BASE (CPU_S3C2410X_PERIPHERAL + 0x17000000)
 
@@ -80,5 +87,8 @@ s3c2410x_init(int sdram_size)
     /* Real time clcok */
     s->rtc = s3c24xx_rtc_init(CPU_S3C2410X_RTC_BASE);
 
+    /* GPIO */
+    s->gpio = s3c24xx_gpio_init(s, CPU_S3C2410X_GPIO_BASE, 
CPU_S3C2410X_IDENT_S3C2410A);
+
     return s;
 }
diff --git a/hw/s3c2440.c b/hw/s3c2440.c
index 91f4341..b53f010 100644
--- a/hw/s3c2440.c
+++ b/hw/s3c2440.c
@@ -13,6 +13,9 @@
 
 #include "s3c2440.h"
 
+/* S3C2440 SoC ID */
+#define CPU_S3C2440_IDENT_S3C2440A 0x32440001
+
 /* Integrated peripherals */
 
 /* SRAM */
@@ -36,6 +39,9 @@
 /* Timer controller */
 #define CPU_S3C2440_TIMERS_BASE (CPU_S3C2440_PERIPHERAL + 0x11000000)
 
+/* GPIO */
+#define CPU_S3C2440_GPIO_BASE (CPU_S3C2440_PERIPHERAL + 0x16000000)
+
 /* Real time clock */
 #define CPU_S3C2440_RTC_BASE (CPU_S3C2440_PERIPHERAL + 0x17000000)
 
@@ -78,5 +84,8 @@ s3c2440_init(int sdram_size)
     /* Real time clcok */
     s->rtc = s3c24xx_rtc_init(CPU_S3C2440_RTC_BASE);
 
+    /* And some GPIO */
+    s->gpio = s3c24xx_gpio_init(s, CPU_S3C2440_GPIO_BASE, 
CPU_S3C2440_IDENT_S3C2440A);
+
     return s;
 }
diff --git a/hw/s3c24xx.h b/hw/s3c24xx.h
index 643d841..b9d8dfe 100644
--- a/hw/s3c24xx.h
+++ b/hw/s3c24xx.h
@@ -33,6 +33,8 @@ typedef struct S3CState_s {
     /* Real time clock */
     struct s3c24xx_rtc_state_s *rtc;
 
+    /* GPIO */
+    struct s3c24xx_gpio_state_s *gpio;
 } S3CState;
 
 
@@ -57,5 +59,10 @@ struct s3c24xx_serial_dev_s *s3c24xx_serial_init(S3CState 
*soc, CharDriverState
 /* Initialise real time clock */
 struct s3c24xx_rtc_state_s *s3c24xx_rtc_init(target_phys_addr_t base_addr);
 
+/* initialise GPIO */
+struct s3c24xx_gpio_state_s *s3c24xx_gpio_init(S3CState *soc, 
target_phys_addr_t base_addr, uint32_t cpu_id);
+
+/* get the qemu interrupt from an eirq number */
+qemu_irq s3c24xx_get_eirq(struct s3c24xx_gpio_state_s *s, int einum);
 
 #endif /* S3C24XX_H */
diff --git a/hw/s3c24xx_gpio.c b/hw/s3c24xx_gpio.c
new file mode 100644
index 0000000..1f9134d
--- /dev/null
+++ b/hw/s3c24xx_gpio.c
@@ -0,0 +1,225 @@
+/* hw/s3c24xx_gpio.c
+ *
+ * Samsung S3C24XX GPIO emulation (mostly for E-INT)
+ *
+ * Copyright 2006, 2007 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+#include "s3c24xx.h"
+
+#define S3C_GPIO_GPECON (0x40)
+#define S3C_GPIO_GPEDAT (0x44)
+#define S3C_GPIO_GPEUP (0x48)
+
+#define S3C_GPIO_EINT_MASK (0xA4)
+#define S3C_GPIO_EINT_PEND (0xA8)
+#define S3C_GPIO_GSTATUS0 (0xAC)
+#define S3C_GPIO_GSTATUS1 (0xB0)
+#define S3C_GPIO_GSTATUS2 (0xB4)
+#define S3C_GPIO_GSTATUS3 (0xB8)
+#define S3C_GPIO_GSTATUS4 (0xBC)
+
+
+#define GPRN(r) (r>>2)
+#define GPR(P) s->gpio_reg[P>>2]
+
+/* GPIO controller state */
+struct s3c24xx_gpio_state_s {
+    uint32_t gpio_reg[47];
+
+    qemu_irq *eirqs; /* gpio external interrupts */
+
+    qemu_irq irqs[6]; /* cpu irqs to cascade */
+};
+
+static void
+s3c24xx_gpio_propogate_eint(struct s3c24xx_gpio_state_s *s)
+{
+    uint32_t ints, i;
+
+    ints = GPR(S3C_GPIO_EINT_PEND) & ~GPR(S3C_GPIO_EINT_MASK);
+
+    /* EINT0 - EINT3 are INT0 - INT3 */
+    for (i=0; i < 4; ++i)
+        qemu_set_irq(s->irqs[i], (ints & (1<<i))?1:0);
+
+    /* EINT4 - EINT7 are INT4 */
+    qemu_set_irq(s->irqs[4], (ints & 0xf0)?1:0);
+
+    /* EINT8 - EINT23 are INT5 */
+    qemu_set_irq(s->irqs[5], (ints & 0x00ffff00)?1:0);
+}
+
+static uint32_t
+gpio_con_to_mask(uint32_t con)
+{
+    uint32_t mask = 0x0;
+    int bit;
+
+    for (bit = 0; bit < 16; bit++) {
+        if (((con >> (bit*2)) & 0x3) == 0x01)
+            mask |= 1 << bit;
+    }
+
+    return mask;
+}
+
+static void
+s3c24xx_gpio_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value)
+{
+    struct s3c24xx_gpio_state_s *s = (struct s3c24xx_gpio_state_s *)opaque;
+    int addr = (addr_ >> 2) & 0x3f;
+
+    if (addr < 0 || addr > 47)
+        addr = 47;
+
+    if (addr == (S3C_GPIO_EINT_MASK>>2))
+        value &= ~0xf; /* cannot mask EINT0-EINT3 */
+
+    if (addr == (S3C_GPIO_EINT_PEND>>2)) {
+        s->gpio_reg[addr] &= ~value;
+    } else {
+        if (addr < (0x80/4) && (addr_ & 0xf) == 0x04) {
+            uint32_t mask = gpio_con_to_mask(s->gpio_reg[addr - 1]);
+
+            value &= mask;
+
+            s->gpio_reg[addr] &= ~mask;
+            s->gpio_reg[addr] |= value;
+        } else
+            s->gpio_reg[addr] = value;
+    }
+
+    if ((addr == (S3C_GPIO_EINT_MASK)>>2) ||
+        (addr == (S3C_GPIO_EINT_PEND)>>2)) {
+        /* A write to the EINT regs leads us to determine the interrupts to
+         * propagate
+         */
+        s3c24xx_gpio_propogate_eint(s);
+    }
+}
+
+static uint32_t
+s3c24xx_gpio_read_f(void *opaque, target_phys_addr_t addr_)
+{
+    struct s3c24xx_gpio_state_s *s = (struct s3c24xx_gpio_state_s *)opaque;
+    uint32_t addr = (addr_ >> 2);
+    uint32_t ret;
+
+    if (addr > GPRN(S3C_GPIO_GSTATUS4))
+        addr = GPRN(S3C_GPIO_GSTATUS4);
+
+    ret = s->gpio_reg[addr];
+
+    if (addr == GPRN(S3C_GPIO_GPEDAT)) {
+        /* IIC pins are special function pins on GPE14 and GPE15. If GPE is is
+         * in input mode make the IIC lines appear to be pulled high. This is
+         * neccissary because OS i2c drivers use this to ensure the I2C bus is
+         * clear.
+         */
+        if ((GPR(S3C_GPIO_GPECON) & (3<<28)) == 0)
+            ret |= 1 << 14;
+
+        if ((GPR(S3C_GPIO_GPECON) & (3<<30)) == 0)
+            ret |= 1 << 15;
+    }
+
+    return ret;
+}
+
+
+static CPUReadMemoryFunc *s3c24xx_gpio_read[] = {
+    &s3c24xx_gpio_read_f,
+    &s3c24xx_gpio_read_f,
+    &s3c24xx_gpio_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_gpio_write[] = {
+    &s3c24xx_gpio_write_f,
+    &s3c24xx_gpio_write_f,
+    &s3c24xx_gpio_write_f,
+};
+
+static void
+s3c24xx_gpio_irq_handler(void *opaque, int n, int level)
+{
+    struct s3c24xx_gpio_state_s *s = (struct s3c24xx_gpio_state_s *)opaque;
+
+    if (level)
+        GPR(S3C_GPIO_EINT_PEND) |= (1<<n);
+
+    s3c24xx_gpio_propogate_eint(s);
+}
+
+static void s3c24xx_gpio_save(QEMUFile *f, void *opaque)
+{
+    struct s3c24xx_gpio_state_s *s = (struct s3c24xx_gpio_state_s *)opaque;
+    int i;
+
+    for (i = 0; i < 47; i ++)
+        qemu_put_be32s(f, &s->gpio_reg[i]);
+}
+
+static int s3c24xx_gpio_load(QEMUFile *f, void *opaque, int version_id)
+{
+    struct s3c24xx_gpio_state_s *s = (struct s3c24xx_gpio_state_s *)opaque;
+    int i;
+
+    for (i = 0; i < 47; i ++)
+        qemu_get_be32s(f, &s->gpio_reg[i]);
+
+    return 0;
+}
+
+struct s3c24xx_gpio_state_s *
+s3c24xx_gpio_init(S3CState *soc, target_phys_addr_t base_addr, uint32_t cpu_id)
+{
+    /* Samsung S3C24XX GPIO
+     *
+     * The primary operation here is the ID register and IRQs
+     */
+    struct s3c24xx_gpio_state_s *s;
+    int tag;
+    int i;
+
+    s = qemu_mallocz(sizeof(struct s3c24xx_gpio_state_s));
+    if (!s)
+        return NULL;
+
+    tag = cpu_register_io_memory(0, s3c24xx_gpio_read, s3c24xx_gpio_write, s);
+    cpu_register_physical_memory(base_addr, 47 * 4, tag);
+    register_savevm("s3c24xx_gpio", 0, 0, s3c24xx_gpio_save, 
s3c24xx_gpio_load, s);
+
+    /* set non zero default values */
+    GPR(0x00) = 0x7fffff;
+    GPR(0x34) = 0xfefc;
+    GPR(0x38) = 0xf000;
+    GPR(0x68) = 0xf800;
+    GPR(0x80) = 0x10330;
+    GPR(0xA4) = 0xfffff0;
+    GPR(S3C_GPIO_GSTATUS1) = cpu_id;
+    GPR(S3C_GPIO_GSTATUS2) = 1;
+    GPR(S3C_GPIO_GSTATUS3) = 0;
+    GPR(S3C_GPIO_GSTATUS4) = 0;
+
+    /* obtain first level IRQs for cascade */
+    for (i = 0; i <= 5; i++) {
+        s->irqs[i] = s3c24xx_get_irq(soc->irq, i);
+    }
+
+    /* EINTs 0-23 -- Only 24, not 48 because EINTs are not level */
+    s->eirqs = qemu_allocate_irqs(s3c24xx_gpio_irq_handler, s, 24);
+
+    return s;
+}
+
+/* get the qemu interrupt from an eirq number */
+qemu_irq
+s3c24xx_get_eirq(struct s3c24xx_gpio_state_s *s, int einum)
+{
+    return s->eirqs[einum];
+}
-- 
1.6.0.4