[Qemu-devel] [PATCH 10/16] Peripheral driver for S3C SOC I2C controller.

[Vincent Sanders]

Signed-off-by: Vincent Sanders <address@hidden>
---
 Makefile.target  |    2 +-
 hw/s3c2410x.c    |    7 ++
 hw/s3c2440.c     |    7 ++
 hw/s3c24xx.h     |    9 ++
 hw/s3c24xx_iic.c |  255 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 279 insertions(+), 1 deletions(-)
 create mode 100644 hw/s3c24xx_iic.c

diff --git a/Makefile.target b/Makefile.target
index 52dcf4c..c9af461 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -649,7 +649,7 @@ OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o 
tusb6010.o usb-musb.o
 OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
 OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o s3c24xx_timers.o
-OBJS+= s3c24xx_serial.o s3c24xx_rtc.o s3c24xx_gpio.o
+OBJS+= s3c24xx_serial.o s3c24xx_rtc.o s3c24xx_gpio.o s3c24xx_iic.o
 OBJS+= s3c2410x.o s3c2440.o
 OBJS+= framebuffer.o
 OBJS+= syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
diff --git a/hw/s3c2410x.c b/hw/s3c2410x.c
index c3b84a0..f3057f8 100644
--- a/hw/s3c2410x.c
+++ b/hw/s3c2410x.c
@@ -40,6 +40,9 @@
 /* Timer controller */
 #define CPU_S3C2410X_TIMERS_BASE (CPU_S3C2410X_PERIPHERAL + 0x11000000)
 
+/* IIC */
+#define CPU_S3C2410X_IIC_BASE (CPU_S3C2410X_PERIPHERAL + 0x14000000)
+
 /* GPIO */
 #define CPU_S3C2410X_GPIO_BASE (CPU_S3C2410X_PERIPHERAL + 0x16000000)
 
@@ -90,5 +93,9 @@ s3c2410x_init(int sdram_size)
     /* GPIO */
     s->gpio = s3c24xx_gpio_init(s, CPU_S3C2410X_GPIO_BASE, 
CPU_S3C2410X_IDENT_S3C2410A);
 
+    /* I2C */
+    s->iic = s3c24xx_iic_init(s3c24xx_get_irq(s->irq, 27),
+                              CPU_S3C2410X_IIC_BASE);
+
     return s;
 }
diff --git a/hw/s3c2440.c b/hw/s3c2440.c
index b53f010..f8d6f63 100644
--- a/hw/s3c2440.c
+++ b/hw/s3c2440.c
@@ -39,6 +39,9 @@
 /* Timer controller */
 #define CPU_S3C2440_TIMERS_BASE (CPU_S3C2440_PERIPHERAL + 0x11000000)
 
+/* IIC */
+#define CPU_S3C2440_IIC_BASE (CPU_S3C2440_PERIPHERAL + 0x14000000)
+
 /* GPIO */
 #define CPU_S3C2440_GPIO_BASE (CPU_S3C2440_PERIPHERAL + 0x16000000)
 
@@ -87,5 +90,9 @@ s3c2440_init(int sdram_size)
     /* And some GPIO */
     s->gpio = s3c24xx_gpio_init(s, CPU_S3C2440_GPIO_BASE, 
CPU_S3C2440_IDENT_S3C2440A);
 
+    /* I2C */
+    s->iic = s3c24xx_iic_init(s3c24xx_get_irq(s->irq, 27),
+                              CPU_S3C2440_IIC_BASE);
+
     return s;
 }
diff --git a/hw/s3c24xx.h b/hw/s3c24xx.h
index b9d8dfe..bb52c00 100644
--- a/hw/s3c24xx.h
+++ b/hw/s3c24xx.h
@@ -35,6 +35,9 @@ typedef struct S3CState_s {
 
     /* GPIO */
     struct s3c24xx_gpio_state_s *gpio;
+
+    /* I2C */
+    struct s3c24xx_i2c_state_s *iic;
 } S3CState;
 
 
@@ -65,4 +68,10 @@ struct s3c24xx_gpio_state_s *s3c24xx_gpio_init(S3CState 
*soc, target_phys_addr_t
 /* get the qemu interrupt from an eirq number */
 qemu_irq s3c24xx_get_eirq(struct s3c24xx_gpio_state_s *s, int einum);
 
+/* Initialise I2c controller */
+struct s3c24xx_i2c_state_s *s3c24xx_iic_init(qemu_irq irq, target_phys_addr_t 
base_addr);
+
+/* aquire bus from controller state */
+i2c_bus *s3c24xx_i2c_bus(struct s3c24xx_i2c_state_s *s);
+
 #endif /* S3C24XX_H */
diff --git a/hw/s3c24xx_iic.c b/hw/s3c24xx_iic.c
new file mode 100644
index 0000000..56945f7
--- /dev/null
+++ b/hw/s3c24xx_iic.c
@@ -0,0 +1,255 @@
+/* hw/s3c24xx_iic.c
+ *
+ * Samsung S3C24XX i2c peripheral emulation
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone, Ben Dooks
+ *  and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+#include "i2c.h"
+
+#include "s3c24xx.h"
+
+/* i2c controller registers */
+#define S3C_IICCON  (0x00)
+#define S3C_IICSTAT (0x04)
+#define S3C_IICADD  (0x08)
+#define S3C_IICDS   (0x0C)
+#define S3C_IICLC   (0x10)
+
+#define S3C_IICCON_ACKEN       (1<<7)
+#define S3C_IICCON_TXDIV_16    (0<<6)
+#define S3C_IICCON_TXDIV_512   (1<<6)
+#define S3C_IICCON_IRQEN       (1<<5)
+#define S3C_IICCON_IRQPEND     (1<<4)
+#define S3C_IICCON_SCALE(x)    ((x)&15)
+#define S3C_IICCON_SCALEMASK   (0xf)
+
+#define S3C_IICSTAT_MASTER_RX  (2<<6)
+#define S3C_IICSTAT_MASTER_TX  (3<<6)
+#define S3C_IICSTAT_SLAVE_RX   (0<<6)
+#define S3C_IICSTAT_SLAVE_TX   (1<<6)
+#define S3C_IICSTAT_MODEMASK   (3<<6)
+
+#define S3C_IICSTAT_START      (1<<5)
+#define S3C_IICSTAT_BUSBUSY    (1<<5)
+#define S3C_IICSTAT_TXRXEN     (1<<4)
+#define S3C_IICSTAT_ARBITR     (1<<3)
+#define S3C_IICSTAT_ASSLAVE    (1<<2)
+#define S3C_IICSTAT_ADDR0       (1<<1)
+#define S3C_IICSTAT_LASTBIT     (1<<0)
+
+#define S3C_IICLC_SDA_DELAY0    (0 << 0)
+#define S3C_IICLC_SDA_DELAY5    (1 << 0)
+#define S3C_IICLC_SDA_DELAY10   (2 << 0)
+#define S3C_IICLC_SDA_DELAY15   (3 << 0)
+#define S3C_IICLC_SDA_DELAY_MASK (3 << 0)
+
+#define S3C_IICLC_FILTER_ON      (1<<2)
+
+/* IIC-bus serial interface */
+struct s3c24xx_i2c_state_s {
+    i2c_bus *bus;
+    qemu_irq irq;
+
+    uint8_t control;
+    uint8_t status;
+    uint8_t data;
+    uint8_t addy;
+    int busy;
+    int newstart;
+};
+
+static void s3c24xx_i2c_irq(struct s3c24xx_i2c_state_s *s)
+{
+    s->control |= 1 << 4;
+
+    if (s->control & (1 << 5)) {
+        qemu_irq_raise(s->irq);
+    }
+}
+
+static void s3c24xx_i2c_reset(struct s3c24xx_i2c_state_s *s)
+{
+    s->control = 0x00;
+    s->status = 0x00;
+    s->busy = 0;
+    s->newstart = 0;
+}
+
+
+static void s3c_master_work(void *opaque)
+{
+    struct s3c24xx_i2c_state_s *s = (struct s3c24xx_i2c_state_s *) opaque;
+    int start = 0, stop = 0, ack = 1;
+
+    if (s->control & (1 << 4))                         /* Interrupt pending */
+        return;
+    if ((s->status & 0x90) != 0x90)                    /* Master */
+        return;
+
+    stop = ~s->status & (1 << 5);
+    if (s->newstart && s->status & (1 << 5)) {         /* START */
+        s->busy = 1;
+        start = 1;
+    }
+    s->newstart = 0;
+
+    if (!s->busy) {
+        return;
+    }
+
+    if (start) {
+        ack = !i2c_start_transfer(s->bus, s->data >> 1, (~s->status >> 6) & 1);
+    } else if (stop) {
+        i2c_end_transfer(s->bus);
+    } else if (s->status & (1 << 6)) {
+        ack = !i2c_send(s->bus, s->data);
+    } else {
+        s->data = i2c_recv(s->bus);
+
+        if (!(s->control & (1 << 7)))                  /* ACK */
+            i2c_nack(s->bus);
+    }
+
+    if (!(s->status & (1 << 5))) {
+        s->busy = 0;
+        return;
+    }
+
+    s->status &= ~1;
+    s->status |= !ack;
+
+    if (!ack) {
+        s->busy = 0;
+    }
+    s3c24xx_i2c_irq(s);
+}
+
+static uint32_t s3c24xx_i2c_read(void *opaque, target_phys_addr_t addr)
+{
+    struct s3c24xx_i2c_state_s *s = (struct s3c24xx_i2c_state_s *) opaque;
+
+    switch (addr) {
+    case S3C_IICCON:
+        return s->control;
+
+    case S3C_IICSTAT:
+        return s->status & ~(1 << 5);                  /* Busy signal */
+
+    case S3C_IICADD:
+        return s->addy;
+
+    case S3C_IICDS:
+        return s->data;
+
+    default:
+        printf("%s: Bad register 0x%lx\n", __func__, addr);
+        break;
+    }
+    return 0;
+}
+
+static void s3c24xx_i2c_write(void *opaque, target_phys_addr_t addr,
+                              uint32_t value)
+{
+    struct s3c24xx_i2c_state_s *s = (struct s3c24xx_i2c_state_s *) opaque;
+
+    switch (addr) {
+    case S3C_IICCON:
+        s->control = (s->control | 0xef) & value;
+        if (s->busy || ((s->control & (1<<4)) == 0))
+            s3c_master_work(s);
+        break;
+
+    case S3C_IICSTAT:
+        s->status &= 0x0f;
+        s->status |= value & 0xf0;
+        if (s->status & (1 << 5))
+            s->newstart = 1;
+        s3c_master_work(s);
+        break;
+
+    case S3C_IICADD:
+        s->addy = value & 0x7f;
+        break;
+
+    case S3C_IICDS:
+        s->data = value & 0xff;
+        s->busy = 1;
+        break;
+
+    default:
+        printf("%s: Bad register 0x%lx\n", __func__, addr);
+        break;
+    }
+}
+
+static CPUReadMemoryFunc *s3c24xx_i2c_readfn[] = {
+    s3c24xx_i2c_read,
+    s3c24xx_i2c_read,
+    s3c24xx_i2c_read,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_i2c_writefn[] = {
+    s3c24xx_i2c_write,
+    s3c24xx_i2c_write,
+    s3c24xx_i2c_write,
+};
+
+static void s3c24xx_i2c_save(QEMUFile *f, void *opaque)
+{
+    struct s3c24xx_i2c_state_s *s = (struct s3c24xx_i2c_state_s *) opaque;
+    qemu_put_8s(f, &s->control);
+    qemu_put_8s(f, &s->status);
+    qemu_put_8s(f, &s->data);
+    qemu_put_8s(f, &s->addy);
+
+    qemu_put_be32(f, s->busy);
+    qemu_put_be32(f, s->newstart);
+
+}
+
+static int s3c24xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
+{
+    struct s3c24xx_i2c_state_s *s = (struct s3c24xx_i2c_state_s *) opaque;
+    qemu_get_8s(f, &s->control);
+    qemu_get_8s(f, &s->status);
+    qemu_get_8s(f, &s->data);
+    qemu_get_8s(f, &s->addy);
+
+    s->busy = qemu_get_be32(f);
+    s->newstart = qemu_get_be32(f);
+
+    return 0;
+}
+
+
+struct s3c24xx_i2c_state_s *
+s3c24xx_iic_init(qemu_irq irq, target_phys_addr_t base_addr)
+{
+    int tag;
+    struct s3c24xx_i2c_state_s *s;
+
+    s = qemu_mallocz(sizeof(struct s3c24xx_i2c_state_s));
+
+    s->irq = irq;
+    s->bus = i2c_init_bus(NULL, "i2c");
+
+    s3c24xx_i2c_reset(s);
+
+    tag = cpu_register_io_memory(0, s3c24xx_i2c_readfn, s3c24xx_i2c_writefn, 
s);
+    cpu_register_physical_memory(base_addr, 0xffffff, tag);
+    register_savevm("s3c24xx_i2c", 0, 0, s3c24xx_i2c_save, s3c24xx_i2c_load, 
s);
+
+    return s;
+}
+
+i2c_bus *s3c24xx_i2c_bus(struct s3c24xx_i2c_state_s *s)
+{
+    return s->bus;
+}
-- 
1.6.0.4