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[Qemu-devel] [PATCH 048/111] m68k: correct shift side effect for roxrl a
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 048/111] m68k: correct shift side effect for roxrl and roxll |
Date: |
Wed, 17 Aug 2011 15:46:53 -0500 |
From: Laurent Vivier <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/helper.c | 10 ++++++++--
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index bdfe9aa..a3a6108 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -915,7 +915,10 @@ uint32_t HELPER(glue(glue(roxr,bits),_cc))(CPUState *env,
uint32_t val, uint32_t
if (bits == 16) count = rox16_table[count]; \
if (bits == 32) count = rox32_table[count]; \
if (count) { \
- result = ((type)val >> count) | ((type)env->cc_x << (bits - count)); \
+ if (count == bits)\
+ result = ((type)env->cc_x << (bits - count));\
+ else \
+ result = ((type)val >> count) | ((type)env->cc_x << (bits -
count));\
if (count > 1) \
result |= (type)val << (bits + 1 - count); \
env->cc_x = ((type)val >> (count - 1)) & 1; \
@@ -947,7 +950,10 @@ uint32_t HELPER(glue(glue(roxl,bits),_cc))(CPUState *env,
uint32_t val, uint32_t
if (bits == 16) count = rox16_table[count]; \
if (bits == 32) count = rox32_table[count]; \
if (count) { \
- result = ((type)val << count) | ((type)env->cc_x << (count - 1)); \
+ if (count == bits) \
+ result = ((type)env->cc_x << (count - 1)); \
+ else \
+ result = ((type)val << count) | ((type)env->cc_x << (count - 1)); \
if (count > 1) \
result |= (type)val >> (bits + 1 - count); \
env->cc_x = ((type)val >> (bits - count)) & 1; \
--
1.7.2.3
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, (continued)
[Qemu-devel] [PATCH 086/111] m68k: correct bfins instruction, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 025/111] m68k: add cas, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 067/111] m68k: add fscale, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 033/111] m68k: Add fmovecr, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 058/111] m68k: correctly compute divul, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 069/111] m68k: add fetox and flogn, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 048/111] m68k: correct shift side effect for roxrl and roxll,
Bryce Lanham <=
[Qemu-devel] [PATCH 065/111] m68k: correct compute gen_bitfield_cc(), Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 049/111] m68k: asl/asr, clear C flag if shift count is 0, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 044/111] m68k: improve addx instructions Add (byte, word) opsize Add memory access, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 046/111] m68k: improve asl/asr evaluate correclty the missing V flag, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 023/111] m68k: add variable offset/width to bitfield_reg/bitfield_mem, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 081/111] m68k: correct fpcr update, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 063/111] m68k: some FPU debugging macros, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 066/111] m68k: add fgetexp, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 051/111] m68k: correct divs.w and divu.w, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 071/111] m68k: correct cmpa comparison datatype, Bryce Lanham, 2011/08/17