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Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts c
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable |
Date: |
Wed, 11 Jan 2012 15:54:50 +0000 |
On 11 January 2012 15:26, Mark Langsdorf <address@hidden> wrote:
> Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020,
> and create a configurable property for each defaulting to 96 and 64
> (respectively) so that device modelers can set the value appropriately
> for their SoC. Other ARM processors also set their maximum number of
> used IRQs appropriately.
>
> Set the maximum theoretically number of GIC interrupts to 1020 and
This patch has lost the typo fix ("theoretical") that was in the
last version. I wouldn't bother mentioning this if not for:
> +static SysBusDeviceInfo armv7m_nvic_priv_info = {
> + .init = armv7m_nvic_init,
> + .qdev.name = "armv7m_nvic",
> + .qdev.size = sizeof(nvic_state),
> + .qdev.vmsd = &vmstate_nvic,
> + .qdev.props = (Property[]) {
> + /* The ARM v7m may have anything from 0 to 496 external interrupt
> + * IRQ lines. We default to 64 external and 32 internal
> + * Other boards may differ and should set this property
> appropriately.
> + */
This is still wrong: from my comments on v5 of this patch:
This comment shouldn't talk about the 32 internal lines, as they are an
implementation detail of arm_gic.c, not architectural (unlike the A
profile GIC internal interrupt lines).
/* The ARM v7m may have anything from 0 to 496 external interrupt
* IRQ lines. We default to 64. Other boards may differ and should
* set this property appropriately.
*/
-- PMM
- [Qemu-devel] [PATCH v8 3/6] ahci: add support for non-PCI based controllers, (continued)
- [Qemu-devel] [PATCH v8 3/6] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v8 4/6] arm: Add dummy support for co-processor 15's secure config register, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v8 1/6] Add xgmac ethernet model, Mark Langsdorf, 2012/01/11
- Re: [Qemu-devel] [PATCH v8 1/6] Add xgmac ethernet model, Peter Maydell, 2012/01/11
- Re: [Qemu-devel] [PATCH v8 1/6] Add xgmac ethernet model, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH v8 5/6] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/11
- Re: [Qemu-devel] [PATCH v8 5/6] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/11
- [Qemu-devel] [PATCH v8 6/6] arm: Remove incorrect comment in arm_timer, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable, Mark Langsdorf, 2012/01/11
- Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable, Andreas Färber, 2012/01/11
- Re: [Qemu-devel] [PATCH v8 2/6] arm: make the number of GIC interrupts configurable,
Peter Maydell <=
[Qemu-devel] [PATCH v9 0/6] arm: add support for Calxeda Highbank SoC, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v9 6/6] arm: Remove incorrect comment in arm_timer, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v9 3/6] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v9 4/6] arm: Add dummy support for co-processor 15's secure config register, Mark Langsdorf, 2012/01/11
- [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/11
- Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Mitsyanko Igor, 2012/01/12
- Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Andreas Färber, 2012/01/12
- Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Mitsyanko Igor, 2012/01/12
- Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/12
Re: [Qemu-devel] [PATCH v9 5/6] arm: SoC model for Calxeda Highbank, Mitsyanko Igor, 2012/01/12