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Re: [Qemu-devel] [PATCH 6/9] target-xtensa: implement FP0 arithmetic
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 6/9] target-xtensa: implement FP0 arithmetic |
Date: |
Sun, 9 Sep 2012 11:05:10 +0100 |
On 9 September 2012 02:29, Max Filippov <address@hidden> wrote:
> +float32 HELPER(abs_s)(float32 v)
> +{
> + return float32_abs(v);
> +}
> +
> +float32 HELPER(neg_s)(float32 v)
> +{
> + return float32_chs(v);
> +}
Given that these are just 'v &= 0x7fffffff' and 'v ^= 0x80000000'
it seems like it would be better to just generate code for them
rather than calling out to a helper, though in some ways it does
break the abstraction layer of the softfloat library. I've been
toying with the idea of doing this for target-arm.
(we could have gen_float32_abs() and gen_float32_chs() in
softfloat.h, or would that be a worse layering violation in
the other direction? I dunno.)
-- PMM
- Re: [Qemu-devel] [PATCH 1/9] softfloat: make float_muladd_negate_* flags independent, (continued)
[Qemu-devel] [PATCH 4/9] target-xtensa: add FP registers, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 5/9] target-xtensa: implement LSCX and LSCI groups, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 6/9] target-xtensa: implement FP0 arithmetic, Max Filippov, 2012/09/08
- Re: [Qemu-devel] [PATCH 6/9] target-xtensa: implement FP0 arithmetic,
Peter Maydell <=
[Qemu-devel] [PATCH 7/9] target-xtensa: implement FP0 conversions, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 8/9] target-xtensa: implement FP1 group, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 9/9] target-xtensa: implement coprocessor context option, Max Filippov, 2012/09/08