[Qemu-devel] [PATCH 30/60] AArch64: Add extr instruction emulation

[Alexander Graf]

This patch adds emulation support for the extr instruction.

Signed-off-by: Alexander Graf <address@hidden>
---
 target-arm/translate-a64.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 63eca24..a314af0 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1143,6 +1143,33 @@ static void handle_orri(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_op2);
 }
 
+static void handle_extr(DisasContext *s, uint32_t insn)
+{
+    int rd = get_reg(insn);
+    int rn = get_bits(insn, 5, 5);
+    int imms = get_bits(insn, 10, 6);
+    int rm = get_bits(insn, 16, 5);
+    bool is_32bit = !get_bits(insn, 31, 1);
+    int bitsize = is_32bit ? 32 : 64;
+    TCGv_i64 tcg_res = tcg_temp_new_i64();
+    TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+
+    if (is_32bit) {
+        tcg_gen_ext32u_i64(tcg_tmp, cpu_reg(rm));
+    } else {
+        tcg_gen_mov_i64(tcg_tmp, cpu_reg(rm));
+    }
+    tcg_gen_shri_i64(tcg_res, cpu_reg(rm), imms);
+    tcg_gen_shli_i64(tcg_tmp, cpu_reg(rn), bitsize - imms);
+    tcg_gen_or_i64(cpu_reg(rd), tcg_tmp, tcg_res);
+    if (is_32bit) {
+        tcg_gen_ext32u_i64(cpu_reg(rd), cpu_reg(rd));
+    }
+
+    tcg_temp_free_i64(tcg_tmp);
+    tcg_temp_free_i64(tcg_res);
+}
+
 /* SIMD ORR */
 static void handle_simdorr(DisasContext *s, uint32_t insn)
 {
@@ -1578,6 +1605,14 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
             handle_orri(s, insn);
         }
         break;
+    case 0x13:
+        if (get_bits(insn, 23, 1) && !get_bits(insn, 21, 1) &&
+            !get_bits(insn, 29, 2)) {
+            handle_extr(s, insn);
+        } else {
+            unallocated_encoding(s);
+        }
+        break;
     default:
         unallocated_encoding(s);
         break;
-- 
1.7.12.4