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Re: [Qemu-devel] [PATCH 29/60] AArch64: Add orri instruction emulation
From: |
Laurent Desnogues |
Subject: |
Re: [Qemu-devel] [PATCH 29/60] AArch64: Add orri instruction emulation |
Date: |
Tue, 26 Nov 2013 13:05:00 +0100 |
On Tue, Nov 26, 2013 at 12:56 PM, Claudio Fontana
<address@hidden> wrote:
> On 09/27/2013 09:42 PM, Richard Henderson wrote:
>> On 09/26/2013 05:48 PM, Alexander Graf wrote:
>>> + if (setflags) {
>>> + tcg_dst = cpu_reg(dest);
>>> + } else {
>>> + tcg_dst = cpu_reg_sp(dest);
>>> + }
>>
>> Never sp for logicals.
>
> This should be ok in my view, the manual explicitly shows in the pseudocode:
>
> if d == 31 && !setflags then
> SP[] = result;
> else
> X[d] = result;
Agreed: for immediate logical instructions, destination can be SP
except for ANDS. ANDS with destination as r31 is aliased to TST.
Laurent
> Claudio
>
>>
>>> + handle_orri(s, insn);
>>
>> And yet again, a better function name.
>>
>>
>> r~
>>
>