[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 48/62] host-utils: add clrsb32/64 - count leading red
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 48/62] host-utils: add clrsb32/64 - count leading redundant sign bits |
Date: |
Tue, 17 Dec 2013 20:29:06 +0000 |
From: Claudio Fontana <address@hidden>
this patch introduces wrappers for the clrsb builtins,
which count the leading redundant sign bits.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
include/qemu/host-utils.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 0f688c1..de85d28 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -228,6 +228,38 @@ static inline int cto64(uint64_t val)
}
/**
+ * clrsb32 - count leading redundant sign bits in a 32-bit value.
+ * @val: The value to search
+ *
+ * Returns the number of bits following the sign bit that are equal to it.
+ * No special cases; output range is [0-31].
+ */
+static inline int clrsb32(uint32_t val)
+{
+#if QEMU_GNUC_PREREQ(4, 7)
+ return __builtin_clrsb(val);
+#else
+ return clz32(val ^ ((int32_t)val >> 1)) - 1;
+#endif
+}
+
+/**
+ * clrsb64 - count leading redundant sign bits in a 64-bit value.
+ * @val: The value to search
+ *
+ * Returns the number of bits following the sign bit that are equal to it.
+ * No special cases; output range is [0-63].
+ */
+static inline int clrsb64(uint64_t val)
+{
+#if QEMU_GNUC_PREREQ(4, 7)
+ return __builtin_clrsbll(val);
+#else
+ return clz64(val ^ ((int64_t)val >> 1)) - 1;
+#endif
+}
+
+/**
* ctpop8 - count the population of one bits in an 8-bit value.
* @val: The value to search
*/
--
1.8.5
- [Qemu-devel] [PULL 40/62] target-arm: A64: add support for ADR and ADRP, (continued)
- [Qemu-devel] [PULL 40/62] target-arm: A64: add support for ADR and ADRP, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 62/62] MAINTAINERS: add myself to maintain allwinner-a10, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 51/62] hw/arm: add very initial support for Canon DIGIC SoC, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 50/62] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 10/62] target-arm: Define and use ARM_FEATURE_CBAR, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 42/62] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 45/62] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 53/62] hw/arm/digic: add timer support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 58/62] hw/timer: add allwinner a10 timer, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 52/62] hw/arm/digic: prepare DIGIC-based boards support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 48/62] host-utils: add clrsb32/64 - count leading redundant sign bits,
Peter Maydell <=
- [Qemu-devel] [PULL 47/62] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 46/62] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 54/62] hw/arm/digic: add UART support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 43/62] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 37/62] target-arm: A64: add support for compare and branch imm, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 59/62] hw/intc: add allwinner A10 interrupt controller, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 39/62] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 38/62] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 55/62] hw/arm/digic: add NOR ROM support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 44/62] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/17