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[Qemu-devel] [PULL 46/62] target-arm: A64: add support for 1-src REV ins
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 46/62] target-arm: A64: add support for 1-src REV insns |
Date: |
Tue, 17 Dec 2013 20:29:04 +0000 |
From: Claudio Fontana <address@hidden>
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 73 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 0ed21fc..3c702a9 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1080,6 +1080,73 @@ static void handle_rbit(DisasContext *s, unsigned int sf,
}
}
+/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
+static void handle_rev64(DisasContext *s, unsigned int sf,
+ unsigned int rn, unsigned int rd)
+{
+ if (!sf) {
+ unallocated_encoding(s);
+ return;
+ }
+ tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
+}
+
+/* C5.6.149 REV with sf==0, opcode==2
+ * C5.6.151 REV32 (sf==1, opcode==2)
+ */
+static void handle_rev32(DisasContext *s, unsigned int sf,
+ unsigned int rn, unsigned int rd)
+{
+ TCGv_i64 tcg_rd = cpu_reg(s, rd);
+
+ if (sf) {
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+ TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
+
+ /* bswap32_i64 requires zero high word */
+ tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
+ tcg_gen_bswap32_i64(tcg_rd, tcg_tmp);
+ tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
+ tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
+ tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);
+
+ tcg_temp_free_i64(tcg_tmp);
+ } else {
+ tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
+ tcg_gen_bswap32_i64(tcg_rd, tcg_rd);
+ }
+}
+
+/* C5.6.150 REV16 (opcode==1) */
+static void handle_rev16(DisasContext *s, unsigned int sf,
+ unsigned int rn, unsigned int rd)
+{
+ TCGv_i64 tcg_rd = cpu_reg(s, rd);
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+ TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
+
+ tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
+ tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
+
+ tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
+ tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
+ tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
+ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
+
+ if (sf) {
+ tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
+ tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
+ tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
+ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);
+
+ tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
+ tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
+ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16);
+ }
+
+ tcg_temp_free_i64(tcg_tmp);
+}
+
/* C3.5.7 Data-processing (1 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+---------+--------+------+------+
@@ -1105,9 +1172,13 @@ static void disas_data_proc_1src(DisasContext *s,
uint32_t insn)
handle_rbit(s, sf, rn, rd);
break;
case 1: /* REV16 */
+ handle_rev16(s, sf, rn, rd);
+ break;
case 2: /* REV32 */
+ handle_rev32(s, sf, rn, rd);
+ break;
case 3: /* REV64 */
- unsupported_encoding(s, insn);
+ handle_rev64(s, sf, rn, rd);
break;
case 4: /* CLZ */
handle_clz(s, sf, rn, rd);
--
1.8.5
- [Qemu-devel] [PULL 51/62] hw/arm: add very initial support for Canon DIGIC SoC, (continued)
- [Qemu-devel] [PULL 51/62] hw/arm: add very initial support for Canon DIGIC SoC, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 50/62] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 10/62] target-arm: Define and use ARM_FEATURE_CBAR, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 42/62] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 45/62] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 53/62] hw/arm/digic: add timer support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 58/62] hw/timer: add allwinner a10 timer, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 52/62] hw/arm/digic: prepare DIGIC-based boards support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 48/62] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 47/62] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 46/62] target-arm: A64: add support for 1-src REV insns,
Peter Maydell <=
- [Qemu-devel] [PULL 54/62] hw/arm/digic: add UART support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 43/62] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 37/62] target-arm: A64: add support for compare and branch imm, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 59/62] hw/intc: add allwinner A10 interrupt controller, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 39/62] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 38/62] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 55/62] hw/arm/digic: add NOR ROM support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 44/62] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 49/62] target-arm: A64: add support for 1-src CLS insn, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 41/62] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/17