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Re: [Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AA
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags |
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Date: |
Tue, 28 Jan 2014 08:42:21 +0000 |
On 28 January 2014 01:28, Peter Crosthwaite
<address@hidden> wrote:
> On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell <address@hidden> wrote:
>> We already implicitly rely on the exception level being
>> part of the TB flags for coprocessor access,
>
> Maybe that's the issue? Why not just treat the exception level as
> state like any other and generate the TCG to just check it at
> execution time?
That would be ferociously expensive, because "am I privileged
or not?" is baked into every single guest load or store.
Including privilege level in the tb flags is standard for
every target CPU we have.
thanks
-- PMM
- Re: [Qemu-devel] [PATCH 19/24] target-arm: Implement AArch64 TTBR*, (continued)
[Qemu-devel] [PATCH 21/24] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 15/24] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs, Peter Maydell, 2014/01/21