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[Qemu-devel] [PATCH 27/28] target-ppc: Altivec 2.07: Vector SHA Sigma In
From: |
Tom Musta |
Subject: |
[Qemu-devel] [PATCH 27/28] target-ppc: Altivec 2.07: Vector SHA Sigma Instructions |
Date: |
Wed, 12 Feb 2014 15:23:18 -0600 |
This patch adds the Vector SHA Sigma instructions introduced in Power
ISA Version 2.07:
- Vector SHA-512 Sigma Doubleword (vshasigmad)
- Vector SHA-256 Sigma Word (vshasigmaw)
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/helper.h | 2 +
target-ppc/int_helper.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 24 ++++++++++++++
3 files changed, 108 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 93e549e..dc0527b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -321,6 +321,8 @@ DEF_HELPER_3(vcipher, void, avr, avr, avr)
DEF_HELPER_3(vcipherlast, void, avr, avr, avr)
DEF_HELPER_3(vncipher, void, avr, avr, avr)
DEF_HELPER_3(vncipherlast, void, avr, avr, avr)
+DEF_HELPER_3(vshasigmaw, void, avr, avr, i32)
+DEF_HELPER_3(vshasigmad, void, avr, avr, i32)
DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index cd04e8a..e6a7ad0 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2618,6 +2618,88 @@ void helper_vncipherlast(ppc_avr_t *r, ppc_avr_t *a,
ppc_avr_t *b)
r->u64[1] = vtemp2.u64[1] ^ b->u64[1];
}
+#define ROTRu32(v, n) (((v) >> (n)) | ((v) << (32-n)))
+#if defined(HOST_WORDS_BIGENDIAN)
+#define EL_IDX(i) (i)
+#else
+#define EL_IDX(i) (3 - (i))
+#endif
+
+void helper_vshasigmaw(ppc_avr_t *r, ppc_avr_t *a, uint32_t st_six)
+{
+ int st = (st_six & 0x10) != 0;
+ int six = st_six & 0xF;
+ int i;
+
+ VECTOR_FOR_INORDER_I(i, u32) {
+ if (st == 0) {
+ if ((six & (0x8 >> i)) == 0) {
+ r->u32[EL_IDX(i)] = ROTRu32(a->u32[EL_IDX(i)], 7) ^
+ ROTRu32(a->u32[EL_IDX(i)], 18) ^
+ (a->u32[EL_IDX(i)] >> 3);
+ } else { /* six.bit[i] == 1 */
+ r->u32[EL_IDX(i)] = ROTRu32(a->u32[EL_IDX(i)], 17) ^
+ ROTRu32(a->u32[EL_IDX(i)], 19) ^
+ (a->u32[EL_IDX(i)] >> 10);
+ }
+ } else { /* st == 1 */
+ if ((six & (0x8 >> i)) == 0) {
+ r->u32[EL_IDX(i)] = ROTRu32(a->u32[EL_IDX(i)], 2) ^
+ ROTRu32(a->u32[EL_IDX(i)], 13) ^
+ ROTRu32(a->u32[EL_IDX(i)], 22);
+ } else { /* six.bit[i] == 1 */
+ r->u32[EL_IDX(i)] = ROTRu32(a->u32[EL_IDX(i)], 6) ^
+ ROTRu32(a->u32[EL_IDX(i)], 11) ^
+ ROTRu32(a->u32[EL_IDX(i)], 25);
+ }
+ }
+ }
+}
+
+#undef ROTRu32
+#undef EL_IDX
+
+#define ROTRu64(v, n) (((v) >> (n)) | ((v) << (64-n)))
+#if defined(HOST_WORDS_BIGENDIAN)
+#define EL_IDX(i) (i)
+#else
+#define EL_IDX(i) (1 - (i))
+#endif
+
+void helper_vshasigmad(ppc_avr_t *r, ppc_avr_t *a, uint32_t st_six)
+{
+ int st = (st_six & 0x10) != 0;
+ int six = st_six & 0xF;
+ int i;
+
+ VECTOR_FOR_INORDER_I(i, u64) {
+ if (st == 0) {
+ if ((six & (0x8 >> (2*i))) == 0) {
+ r->u64[EL_IDX(i)] = ROTRu64(a->u64[EL_IDX(i)], 1) ^
+ ROTRu64(a->u64[EL_IDX(i)], 8) ^
+ (a->u64[EL_IDX(i)] >> 7);
+ } else { /* six.bit[2*i] == 1 */
+ r->u64[EL_IDX(i)] = ROTRu64(a->u64[EL_IDX(i)], 19) ^
+ ROTRu64(a->u64[EL_IDX(i)], 61) ^
+ (a->u64[EL_IDX(i)] >> 6);
+ }
+ } else { /* st == 1 */
+ if ((six & (0x8 >> (2*i))) == 0) {
+ r->u64[EL_IDX(i)] = ROTRu64(a->u64[EL_IDX(i)], 28) ^
+ ROTRu64(a->u64[EL_IDX(i)], 34) ^
+ ROTRu64(a->u64[EL_IDX(i)], 39);
+ } else { /* six.bit[2*i] == 1 */
+ r->u64[EL_IDX(i)] = ROTRu64(a->u64[EL_IDX(i)], 14) ^
+ ROTRu64(a->u64[EL_IDX(i)], 18) ^
+ ROTRu64(a->u64[EL_IDX(i)], 41);
+ }
+ }
+ }
+}
+
+#undef ROTRu64
+#undef EL_IDX
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fe98367..e48d756 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7436,6 +7436,27 @@ GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
+#define VSHASIGMA(op) \
+static void gen_##op(DisasContext *ctx) \
+{ \
+ TCGv_ptr ra, rd; \
+ TCGv_i32 st_six; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ st_six = tcg_const_i32(rB(ctx->opcode)); \
+ gen_helper_##op(rd, ra, st_six); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rd); \
+ tcg_temp_free_i32(st_six); \
+}
+
+VSHASIGMA(vshasigmaw)
+VSHASIGMA(vshasigmad)
+
/*** VSX extension ***/
static inline TCGv_i64 cpu_vsrh(int n)
@@ -10671,6 +10692,9 @@ GEN_VXFORM_207(vsbox, 4, 23),
GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_207(vshasigmaw, 1, 26),
+GEN_VXFORM_207(vshasigmad, 1, 27),
+
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
--
1.7.1
- [Qemu-devel] [PATCH 24/28] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum, (continued)
[Qemu-devel] [PATCH 27/28] target-ppc: Altivec 2.07: Vector SHA Sigma Instructions,
Tom Musta <=
[Qemu-devel] [PATCH 28/28] target-ppc: Altivec 2.07: Vector Permute and Exclusive OR, Tom Musta, 2014/02/12
Re: [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07, Richard W.M. Jones, 2014/02/18
- Re: [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07, Tom Musta, 2014/02/18
- Re: [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07, Richard W.M. Jones, 2014/02/20
- Re: [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07, Richard W.M. Jones, 2014/02/20
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/28] target-ppc: Altivec 2.07, Alexander Graf, 2014/02/20
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/28] target-ppc: Altivec 2.07, Richard W.M. Jones, 2014/02/20
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/28] target-ppc: Altivec 2.07, Aneesh Kumar K.V, 2014/02/21
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/28] target-ppc: Altivec 2.07, Avik Sil, 2014/02/21
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/28] target-ppc: Altivec 2.07, Alexander Graf, 2014/02/21