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[Qemu-devel] [RFC 3/4] Add l2ctlr cp register to CPUARMState
From: |
Alvise Rigo |
Subject: |
[Qemu-devel] [RFC 3/4] Add l2ctlr cp register to CPUARMState |
Date: |
Tue, 25 Feb 2014 17:52:49 +0100 |
Since the irq bit seems to not be updated, exclude it from the check done
while copying data during migration.
Signed-off-by: Alvise Rigo <address@hidden>
---
target-arm/cpu.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 6e7ce89..e8db00e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -681,20 +681,34 @@ static void cortex_a9_initfn(Object *obj)
}
#ifndef CONFIG_USER_ONLY
-static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+static void a15_l2ctlr_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
{
/* Linux wants the number of processors from here.
* Might as well set the interrupt-controller bit too.
*/
- return ((smp_cpus - 1) << 24) | (1 << 23);
+ env->cp15.c9_l2ctlr = ((smp_cpus - 1) << 24) | (1 << 23);
+}
+
+static void a15_l2ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ int smp_cpus_new = ((value >> 24) & 3);
+ int smp_cpus_old = ((env->cp15.c9_l2ctlr >> 24) & 3);
+
+ if (smp_cpus_new != smp_cpus_old) {
+ return;
+ }
+
+ env->cp15.c9_l2ctlr = value;
}
#endif
static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
- .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
- .writefn = arm_cp_write_ignore, },
+ .access = PL1_RW, .resetvalue = 0,
+ .resetfn = a15_l2ctlr_reset, .writefn = a15_l2ctlr_write,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_l2ctlr) },
#endif
{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
--
1.8.3.2
[Qemu-devel] [RFC 4/4] Relevant changes to enable KVM to TCG migration, Alvise Rigo, 2014/02/25