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[Qemu-devel] [PULL 22/26] target-arm: A64: Generalize ERET to various EL
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/26] target-arm: A64: Generalize ERET to various ELs |
Date: |
Tue, 27 May 2014 17:28:30 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Adds support for ERET to and from AArch64 EL2 and 3.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/op_helper.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index e95a7f4..50a4157 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -386,13 +386,13 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op,
uint32_t imm)
void HELPER(exception_return)(CPUARMState *env)
{
- unsigned int spsr_idx = aarch64_banked_spsr_index(1);
+ int cur_el = arm_current_pl(env);
+ unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
uint32_t spsr = env->banked_spsr[spsr_idx];
int new_el, i;
- int cur_el = arm_current_pl(env);
if (env->pstate & PSTATE_SP) {
- env->sp_el[1] = env->xregs[31];
+ env->sp_el[cur_el] = env->xregs[31];
} else {
env->sp_el[0] = env->xregs[31];
}
@@ -400,6 +400,7 @@ void HELPER(exception_return)(CPUARMState *env)
env->exclusive_addr = -1;
if (spsr & PSTATE_nRW) {
+ /* TODO: We currently assume EL1/2/3 are running in AArch64. */
env->aarch64 = 0;
new_el = 0;
env->uncached_cpsr = 0x10;
@@ -429,7 +430,7 @@ void HELPER(exception_return)(CPUARMState *env)
env->aarch64 = 1;
pstate_write(env, spsr);
env->xregs[31] = env->sp_el[new_el];
- env->pc = env->elr_el[1];
+ env->pc = env->elr_el[cur_el];
}
return;
@@ -443,7 +444,7 @@ illegal_return:
* no change to exception level, execution state or stack pointer
*/
env->pstate |= PSTATE_IL;
- env->pc = env->elr_el[1];
+ env->pc = env->elr_el[cur_el];
spsr &= PSTATE_NZCV | PSTATE_DAIF;
spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
pstate_write(env, spsr);
--
1.9.2
- [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 01/26] MAINTAINERS: update Calxeda Highbank maintainer and status, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 12/26] target-arm: A64: Add SP entries for EL2 and 3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 11/26] target-arm: c12_vbar -> vbar_el[], Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 26/26] target-arm: A64: Register VBAR_EL3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 10/26] target-arm: Make esr_el1 an array, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 24/26] target-arm: Make vbar_write writeback to any CPREG, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 22/26] target-arm: A64: Generalize ERET to various ELs,
Peter Maydell <=
- [Qemu-devel] [PULL 21/26] target-arm: A64: Trap ERET from EL0 at translation time, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 17/26] target-arm: Add a feature flag for EL3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 18/26] target-arm: Register EL2 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 19/26] target-arm: Register EL3 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 16/26] target-arm: Add a feature flag for EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 15/26] target-arm: A64: Introduce aarch64_banked_spsr_index(), Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 23/26] target-arm: A64: Generalize update_spsel for the various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 25/26] target-arm: A64: Register VBAR_EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 08/26] target-arm: Use a 1:1 mapping between EL and MMU index, Peter Maydell, 2014/05/27