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[Qemu-devel] [PATCH v5 12/15] target-tricore: Add instructions of SBR op
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v5 12/15] target-tricore: Add instructions of SBR opcode format |
Date: |
Wed, 13 Aug 2014 13:07:21 +0100 |
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-tricore/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 87b5ad3..8e468bd 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -386,6 +386,18 @@ static inline void gen_branch_condi(DisasContext *ctx,
TCGCond cond, TCGv r1,
tcg_temp_free(temp);
}
+static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
+{
+ int l1;
+ l1 = gen_new_label();
+
+ tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
+ gen_goto_tb(ctx, 1, ctx->pc + offset);
+ gen_set_label(l1);
+ gen_goto_tb(ctx, 0, ctx->next_pc);
+}
+
static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
int r2 , int32_t constant , int32_t offset)
{
@@ -427,8 +439,44 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t
opc, int r1,
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
tcg_temp_free(temp);
break;
+/* SBR-format jumps */
+ case OPC1_16_SBR_JEQ:
+ gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
+ offset);
+ break;
+ case OPC1_16_SBR_JNE:
+ gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
+ offset);
+ break;
+ case OPC1_16_SBR_JNZ:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JNZ_A:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JGEZ:
+ gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JGTZ:
+ gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JLEZ:
+ gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JLTZ:
+ gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JZ:
+ gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JZ_A:
+ gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_LOOP:
+ gen_loop(ctx, r1, offset * 2 - 32);
+ break;
default:
- printf("Branch Error at %x\n", ctx->pc);
+ printf("Branch Error at %x\n", ctx->pc);
}
ctx->bstate = BS_BRANCH;
}
@@ -750,6 +798,22 @@ static void decode_16Bit_opc(CPUTRICOREState *env,
DisasContext *ctx)
const16 = MASK_OP_SBRN_N(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
break;
+/* SBR-format */
+ case OPC1_16_SBR_JEQ:
+ case OPC1_16_SBR_JGEZ:
+ case OPC1_16_SBR_JGTZ:
+ case OPC1_16_SBR_JLEZ:
+ case OPC1_16_SBR_JLTZ:
+ case OPC1_16_SBR_JNE:
+ case OPC1_16_SBR_JNZ:
+ case OPC1_16_SBR_JNZ_A:
+ case OPC1_16_SBR_JZ:
+ case OPC1_16_SBR_JZ_A:
+ case OPC1_16_SBR_LOOP:
+ r1 = MASK_OP_SBR_S2(ctx->opcode);
+ address = MASK_OP_SBR_DISP4(ctx->opcode);
+ gen_compute_branch(ctx, op1, r1, 0, 0, address);
+ break;
}
}
--
2.0.4
- Re: [Qemu-devel] [PATCH v5 04/15] target-tricore: Add initialization for translation and activate target, (continued)
- [Qemu-devel] [PATCH v5 05/15] target-tricore: Add masks and opcodes for decoding, Bastian Koppelmann, 2014/08/13
- [Qemu-devel] [PATCH v5 01/15] target-tricore: Add target stubs and qom-cpu, Bastian Koppelmann, 2014/08/13
- [Qemu-devel] [PATCH v5 02/15] target-tricore: Add board for systemmode, Bastian Koppelmann, 2014/08/13
- [Qemu-devel] [PATCH v5 15/15] target-tricore: Add instructions of SR opcode format, Bastian Koppelmann, 2014/08/13
- [Qemu-devel] [PATCH v5 10/15] target-tricore: Add instructions of SB opcode format, Bastian Koppelmann, 2014/08/13
- [Qemu-devel] [PATCH v5 12/15] target-tricore: Add instructions of SBR opcode format,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v5 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format, Bastian Koppelmann, 2014/08/13
- [Qemu-devel] [PATCH v5 03/15] target-tricore: Add softmmu support, Bastian Koppelmann, 2014/08/13
- Re: [Qemu-devel] [PATCH v5 00/15] TriCore architecture guest implementation, Bastian Koppelmann, 2014/08/20
- Re: [Qemu-devel] [PATCH v5 00/15] TriCore architecture guest implementation, Andreas Färber, 2014/08/20