Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

[Pierre Mallard]

On Wed, Sep 10, 2014 at 7:15 PM, Tom Musta <address@hidden> wrote:

(1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer Conversion instructions.

There is also fcfids and fcfidus which leads to 8 instructions (fcfid, fcfids, fcfidu, fcfidus and fctid, fctidz, fctidu, fctiduz), is this right ?

(2) Defined a new flag for FP Signed Doubleword Conversion instructions (PPC2_FP_CVT_S64).  Use this flag exclusively when defining the opcode tables, e.g.

+/* fctidz */
+GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);

I'm not sure, I did understand correctly that one, indeed to have the flag check I have to make changes for each of the three instructions (fcfid, fctif, fctidz) at 2 places in translate.c :

One at the gen_XXXX function definition which is quite straight forward :

GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);

becomes

GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);

One in the Opcode Table which requires to use the GEN_HANDLER_E macro for the second type to be taken in account :

GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64),

becomes

GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64)

is this right ?

 

(3) You would have to add the flag to all existing 64-bit CPUs that support floating point.  And of course, to your new 440-w-fpu CPU.

 

Pierre