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Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn |
Date: |
Fri, 26 Sep 2014 09:31:19 +1000 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Fri, Sep 26, 2014 at 12:17:59AM +0100, Peter Maydell wrote:
> On 25 September 2014 23:55, Edgar E. Iglesias <address@hidden> wrote:
> > On Thu, Sep 25, 2014 at 07:47:16PM +0100, Peter Maydell wrote:
> >> > + /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
> >> > */
> >> > + if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
> >> > + env->exception.syndrome = syndrome;
> >> > + raise_exception(env, EXCP_SMC);
> >>
> >> Shouldn't this just be returning so that the generated
> >> code immediately following can raise the SMC exception
> >> with the correct syndrome, PC and singlestep state?
> >> (would also save you passing in the syndrome argument
> >> to this fn).
> >
> > When routing SMCs to EL2, the exception happens before advancing the
> > PC. It's similar to the undef cases for HVC (and SMC).
>
> Oh, yes, that's the trap enable bit. In that case we shouldn't
> be using EXCP_SMC: this isn't routing the SMC exception, it's
> taking a Hyp trap exception, and in AArch32 the vector
> entry point is different. (Granted, you can't get to AArch32
> by taking an exception from AArch64, but we should use the
> right EXCP_ value to avoid the code looking gratuitously
> different for the two cases.)
I see. I hadn't thought much about the AArch32 case here. For
AArch64, the pseudo code referes to this as route_to_el2.
Anyway, your comment makes sense to avoid diff between a32/a64
and I think it actually makes the AArch64 code a bit cleaner
aswell.
I'll add EXCP_HYP_TRAP.
Thanks,
Edgar
- Re: [Qemu-devel] [PATCH v6 07/10] target-arm: A64: Emulate the HVC insn, (continued)
[Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/13
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Greg Bellows, 2014/09/17
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Peter Maydell, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Peter Maydell, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn,
Edgar E. Iglesias <=
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Peter Maydell, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/25
- Re: [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/26
[Qemu-devel] [PATCH v6 09/10] target-arm: Add IRQ and FIQ routing to EL2 and 3, Edgar E. Iglesias, 2014/09/13
[Qemu-devel] [PATCH v6 10/10] target-arm: Add support for VIRQ and VFIQ, Edgar E. Iglesias, 2014/09/13