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[Qemu-devel] [PATCH target-arm v2 01/13] arm: Do not define TLBTR in PMS
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v2 01/13] arm: Do not define TLBTR in PMSA systems |
Date: |
Fri, 12 Jun 2015 12:10:23 -0700 |
If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP.
The def is done separately from VMSA registers group as it is affected
by both the OMAP/STRONGARM RW errata and the MIDR backgrounding.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3da0c05..1e5c4c1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3448,11 +3448,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "TCMTR",
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "TLBTR",
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
+ /* TLBTR is specific to VMSA */
+ ARMCPRegInfo id_tlbtr_reginfo = {
+ .name = "TLBTR",
+ .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
+ };
ARMCPRegInfo crn0_wi_reginfo = {
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
@@ -3474,6 +3477,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
r->access = PL1_RW;
}
+ id_tlbtr_reginfo.access = PL1_RW;
}
if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
@@ -3481,6 +3485,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
}
define_arm_cp_regs(cpu, id_cp_reginfo);
+ if (!arm_feature(env, ARM_FEATURE_MPU)) {
+ define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
+ }
}
if (arm_feature(env, ARM_FEATURE_MPIDR)) {
--
2.4.3.3.g905f831
- [Qemu-devel] [PATCH target-arm v2 00/13] ARM Cortex R5 Support, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 01/13] arm: Do not define TLBTR in PMSA systems,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v2 02/13] arm: Don't add v7mp registers in MPU systems, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 03/13] arm: helper: Factor out CP regs common to [pv]msa, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 04/13] arm: Refactor get_phys_addr FSR return mechanism, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 05/13] arm: Implement uniprocessor with MP config, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 06/13] arm: Add has-mpu property, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 07/13] target-arm/helper.c: define MPUIR register, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 08/13] arm: helper: rename get_phys_addr_mpu, Peter Crosthwaite, 2015/06/12