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[Qemu-devel] [PULL 03/27] target-arm: Rename and move gt_cnt_reset
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/27] target-arm: Rename and move gt_cnt_reset |
Date: |
Thu, 13 Aug 2015 11:44:23 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Rename gt_cnt_reset to gt_timer_reset as the function really
resets the timers and not the counters. Move the registration
from counter regs to timer regs.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3f8d06e..8dee980 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1261,7 +1261,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
}
}
-static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int timeridx = ri->opc1 & 1;
@@ -1414,7 +1414,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
.type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
- .accessfn = gt_ptimer_access,
+ .accessfn = gt_ptimer_access, .resetfn = gt_timer_reset,
.readfn = gt_tval_read, .writefn = gt_tval_write,
},
{ .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
@@ -1425,7 +1425,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
.type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
- .accessfn = gt_vtimer_access,
+ .accessfn = gt_vtimer_access, .resetfn = gt_timer_reset,
.readfn = gt_tval_read, .writefn = gt_tval_write,
},
/* The counter itself */
@@ -1437,8 +1437,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
.access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
- .accessfn = gt_pct_access,
- .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
+ .accessfn = gt_pct_access, .readfn = gt_cnt_read,
},
{ .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
.access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
@@ -1448,8 +1447,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
.access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
- .accessfn = gt_vct_access,
- .readfn = gt_virt_cnt_read, .resetfn = gt_cnt_reset,
+ .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
},
/* Comparison value, indicating when the timer goes off */
{ .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
--
1.9.1
- [Qemu-devel] [PULL 24/27] target-arm: Add AArch32 banked register access to secure physical timer, (continued)
- [Qemu-devel] [PULL 24/27] target-arm: Add AArch32 banked register access to secure physical timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 10/27] i.MX:Fix Coding style for UART emulator., Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 20/27] hw/arm/gic: Kill code duplication, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 06/27] hw/arm/virt: Replace magic IRQ constants with macros, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 19/27] Merge memory_region_init_reservation() into memory_region_init_io(), Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 02/27] target-arm: Add CNTHCTL_EL2, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 14/27] i.MX: Fix Coding style for CCM emulator, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 27/27] i.MX: Fix UART driver to work with unitialized "chardev" device, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 07/27] hw/arm/virt: Connect the Hypervisor timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 11/27] i.MX: Split AVIC emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 03/27] target-arm: Rename and move gt_cnt_reset,
Peter Maydell <=
- [Qemu-devel] [PULL 13/27] i.MX: Split CCM emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 08/27] i.MX: Split UART emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 05/27] target-arm: Add the Hypervisor timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 21/27] Introduce gic_class_name() instead of repeating condition, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 25/27] hw/arm/virt: Wire up secure timer interrupt, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 09/27] i.MX: Move serial initialization to init/realize of DeviceClass., Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 26/27] hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 04/27] target-arm: Pass timeridx as argument to various timer functions, Peter Maydell, 2015/08/13
- Re: [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/08/13