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[Qemu-devel] [PATCH 0/9] target-arm: Implement A64 semihosting
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 0/9] target-arm: Implement A64 semihosting |
Date: |
Thu, 13 Aug 2015 17:35:36 +0100 |
This patch series implements support for semihosting for the
64-bit ARM instruction set.
It owes a significant debt to the patches sent earlier
by Christopher Covington (and with code written by Derek Hower).
However, it is a full from-scratch rewrite (since there were
several things which I felt those patches didn't take the
right approach on). I mostly just looked at the earlier
patches to check I hadn't missed anything.
The changes in the A64 API compared to the A32/T32 one are:
* input syscall number is in register W0
* return result is in register X0
* all argument parameter blocks are 64 bits wide, not 32
* there is a new SyncCacheRange syscall
* the SYS_EXIT syscall takes a parameter block and is able
to pass a guest exit status out
* the insn used to trigger semihosting is a HLT, not an
SVC or BKPT.
I've tested this for A32, T32 and A64 semihosting, for
both usermode and system emulation, with and without gdb
remote syscalls.
The test code I wrote to do the testing is here:
https://git.linaro.org/people/peter.maydell/semihosting-tests.git/
(not very exciting, but might be handy if anybody needs a
basic "how to run C code starting with bare metal system
emulation" template.)
The test series also includes a bugfix: we haven't correctly
forwarded SYS_WRITE0 (print string to terminal) to gdb since
the gdb hosted syscall support was added to QEMU back in 2007...
Christopher Covington (1):
target-arm: Improve semihosting debug prints
Peter Maydell (8):
target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
gdbstub: Implement gdb_do_syscallv()
target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
include/exec/softmmu-semi.h: Add support for 64-bit values
target-arm/arm-semi.c: Support widening APIs to 64 bits
target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
gdbstub.c | 14 ++--
include/exec/gdbstub.h | 27 +++++++
include/exec/softmmu-semi.h | 18 +++++
linux-user/main.c | 3 +
target-arm/arm-semi.c | 171 +++++++++++++++++++++++++++++++++-----------
target-arm/cpu.h | 3 +-
target-arm/helper-a64.c | 6 ++
target-arm/helper.c | 12 +++-
target-arm/internals.h | 2 +
target-arm/translate-a64.c | 14 +++-
10 files changed, 217 insertions(+), 53 deletions(-)
--
1.9.1
- [Qemu-devel] [PATCH 0/9] target-arm: Implement A64 semihosting,
Peter Maydell <=
- [Qemu-devel] [PATCH 2/9] target-arm: Improve semihosting debug prints, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 5/9] include/exec/softmmu-semi.h: Add support for 64-bit values, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 8/9] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 6/9] target-arm/arm-semi.c: Support widening APIs to 64 bits, Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 3/9] gdbstub: Implement gdb_do_syscallv(), Peter Maydell, 2015/08/13
- [Qemu-devel] [PATCH 1/9] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb, Peter Maydell, 2015/08/13