Re: [Qemu-devel] [PATCH v1 02/10] target-arm: Correct opc1 for AT_S12Exx

[Alistair Francis]

On Thu, Sep 3, 2015 at 1:14 PM, Edgar E. Iglesias
<address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Thanks,

Alistair

> ---
>  target-arm/helper.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 7df1f06..4234e7c 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2975,16 +2975,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
>        .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
>      { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
> -      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 4,
> +      .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
>        .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
>      { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
> -      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 5,
> +      .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
>        .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
>      { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
> -      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
> +      .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
>        .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
>      { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
> -      .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 7,
> +      .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
>        .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
>      /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
>      { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
> --
> 1.9.1
>
>