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[Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield |
Date: |
Mon, 14 Sep 2015 14:52:58 +0100 |
From: Richard Henderson <address@hidden>
For !SF, this initial ext32u can't be optimized away by the
current TCG code generator. (It would require backward bit
liveness propagation.)
But since the range of bits for !SF are already constrained by
unallocated_encoding, we'll never reference the high bits anyway.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index f2f8443..3ab0b42 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3015,7 +3015,11 @@ static void disas_bitfield(DisasContext *s, uint32_t
insn)
}
tcg_rd = cpu_reg(s, rd);
- tcg_tmp = read_cpu_reg(s, rn, sf);
+
+ /* Suppress the zero-extend for !sf. Since RI and SI are constrained
+ to be smaller than bitsize, we'll never reference data outside the
+ low 32-bits anyway. */
+ tcg_tmp = read_cpu_reg(s, rn, 1);
/* Recognize the common aliases. */
if (opc == 0) { /* SBFM */
--
1.9.1
- [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 23/24] target-arm: Break out mpidr_read_val(), Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 24/24] target-arm: Add VMPIDR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 20/24] target-arm: Suppress TBI for S2 translations, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 21/24] target-arm: Suppress EPD for S2, EL2 and EL3 translations, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 22/24] target-arm: Add VPIDR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 17/24] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 13/24] target-arm: Use tcg_gen_extrh_i64_i32, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield,
Peter Maydell <=
- [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 12/24] target-arm: Recognize ROR, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 06/24] target-arm: Use setcond and movcond for csel, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 15/24] i.MX: Add GPIO devices to i.MX31 SOC, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 03/24] target-arm: Share all common TCG temporaries, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 01/24] arm: xlnx-zynqmp: Fix up GIC region size, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 05/24] target-arm: Handle always condition codes within arm_test_cc, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 14/24] i.MX: Add GPIO device, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 10/24] target-arm: Recognize UXTB, UXTH, LSR, LSL, Peter Maydell, 2015/09/14