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Re: [Qemu-devel] [PATCH v2 14/26] armv7m: prevent unprivileged write to
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 14/26] armv7m: prevent unprivileged write to STIR |
Date: |
Thu, 17 Dec 2015 19:33:36 +0000 |
On 3 December 2015 at 00:18, Michael Davidsaver <address@hidden> wrote:
> Prevent unprivileged from writing to the
"unprivileged writes to the"
> Software Triggered Interrupt register
".".
> ---
> hw/intc/armv7m_nvic.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 0f9ca6a..5731146 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -727,7 +727,9 @@ static void nvic_writel(NVICState *s, uint32_t offset,
> uint32_t value)
> "NVIC: Aux fault status registers unimplemented\n");
> break;
> case 0xf00: /* Software Triggered Interrupt Register */
> - if ((value & 0x1ff) < NVIC_MAX_IRQ) {
> + /* STIR write allowed if privlaged or USERSETMPEND set */
You'll want to use the #define of CCR_USERSETMPEND that you'll
add to the previous patch. If you do that then the comment is
no longer really needed as the code itself is fairly straightforward.
(If you want to keep it then "privileged".)
> + if ((arm_current_el(&cpu->env) || (cpu->env.v7m.ccr & 2))
> + && ((value & 0x1ff) < NVIC_MAX_IRQ)) {
> armv7m_nvic_set_pending(s, (value&0x1ff)+16);
> }
> break;
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v2 07/26] armv7m: simpler/faster exception start, (continued)
- [Qemu-devel] [PATCH v2 10/26] armv7m: auto-clear FAULTMASK, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 09/26] armv7m: implement CFSR, HFSR, BFAR, and MMFAR, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 11/26] arm: gic: Remove references to NVIC, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 12/26] armv7m: check exception return consistency, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 14/26] armv7m: prevent unprivileged write to STIR, Michael Davidsaver, 2015/12/02
- Re: [Qemu-devel] [PATCH v2 14/26] armv7m: prevent unprivileged write to STIR,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 13/26] armv7m: implement CCR, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 18/26] armv7m: update base region policy, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 17/26] armv7m: mpu background miss is perm fault, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 23/26] qom: add cpu_generic_init_unrealized(), Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 25/26] armv7m: remove extra cpu_reset(), Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 24/26] armv7m: split armv7m_init in two parts, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 21/26] armv7m: CONTROL<1> handling, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 26/26] armv7m: decide whether faults are MemManage or BusFault, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 08/26] armv7m: rewrite NVIC, Michael Davidsaver, 2015/12/02