[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 36/36] target-arm: Implement FPEXC32_EL2 system regis
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 36/36] target-arm: Implement FPEXC32_EL2 system register |
Date: |
Thu, 21 Jan 2016 14:56:29 +0000 |
The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3,
and allows those exception levels to read and write the FPEXC
register for a lower exception level that is using AArch32.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 06eb775..ae02486 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2891,6 +2891,17 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
tlb_flush(CPU(cpu), 1);
}
+static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ if (env->cp15.cptr_el[3] & CPTR_TFP) {
+ return CP_ACCESS_TRAP_EL3;
+ }
+ return CP_ACCESS_OK;
+}
+
static const ARMCPRegInfo v8_cp_reginfo[] = {
/* Minimal set of EL0-visible registers. This will need to be expanded
* significantly for system emulation of AArch64 CPUs.
@@ -3151,6 +3162,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
.type = ARM_CP_NO_RAW,
.access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
+ { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
+ .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
+ .access = PL2_RW, .accessfn = fpexc32_access },
REGINFO_SENTINEL
};
--
1.9.1
- [Qemu-devel] [PULL 33/36] target-arm: Handle exception return from AArch64 to non-EL0 AArch32, (continued)
- [Qemu-devel] [PULL 33/36] target-arm: Handle exception return from AArch64 to non-EL0 AArch32, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 31/36] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 28/36] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 20/36] target-arm: Add QOM property for Secure memory region, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 23/36] target-arm: Support multiple address spaces in page table walks, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 29/36] target-arm: Move aarch64_cpu_do_interrupt() to helper.c, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 26/36] hw/arm/virt: Add always-on property to the virt board timer, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 30/36] target-arm: Use a single entry point for AArch64 and AArch32 exceptions, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 36/36] target-arm: Implement FPEXC32_EL2 system register,
Peter Maydell <=
- [Qemu-devel] [PULL 08/36] exec.c: Don't set cpu->as until cpu_address_space_init, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 18/36] memory: Add address_space_init_shareable(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 24/36] hw/arm/virt: Wire up memory region to CPUs explicitly, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 12/36] cpu: Add new asidx_from_attrs() method, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 16/36] exec.c: Use cpu_get_phys_page_attrs_debug, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 14/36] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 21/36] target-arm: Implement asidx_from_attrs, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 01/36] qdev: get_child_bus(): Use QOM lookup if available, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 19/36] qom/cpu: Add MemoryRegion property, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 25/36] hw/arm/virt: add secure memory region and UART, Peter Maydell, 2016/01/21