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[Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision |
Date: |
Thu, 21 Jan 2016 14:56:20 +0000 |
From: Alistair Francis <address@hidden>
Update the GIC ID registers (registers above 0xfe0) based on the GIC
revision instead of using the sames values for all GIC implementations.
Signed-off-by: Alistair Francis <address@hidden>
Tested-by: Sören Brinkmann <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 35 ++++++++++++++++++++++++++++++-----
1 file changed, 30 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 13e297d..cd60176 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -31,8 +31,16 @@ do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); }
while (0)
#define DPRINTF(fmt, ...) do {} while(0)
#endif
-static const uint8_t gic_id[] = {
- 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
+static const uint8_t gic_id_11mpcore[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
+};
+
+static const uint8_t gic_id_gicv1[] = {
+ 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
+};
+
+static const uint8_t gic_id_gicv2[] = {
+ 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
};
static inline int gic_get_current_cpu(GICState *s)
@@ -683,14 +691,31 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr
offset, MemTxAttrs attrs)
}
res = s->sgi_pending[irq][cpu];
- } else if (offset < 0xfe0) {
+ } else if (offset < 0xfd0) {
goto bad_reg;
- } else /* offset >= 0xfe0 */ {
+ } else if (offset < 0x1000) {
if (offset & 3) {
res = 0;
} else {
- res = gic_id[(offset - 0xfe0) >> 2];
+ switch (s->revision) {
+ case REV_11MPCORE:
+ res = gic_id_11mpcore[(offset - 0xfd0) >> 2];
+ break;
+ case 1:
+ res = gic_id_gicv1[(offset - 0xfd0) >> 2];
+ break;
+ case 2:
+ res = gic_id_gicv2[(offset - 0xfd0) >> 2];
+ break;
+ case REV_NVIC:
+ /* Shouldn't be able to get here */
+ abort();
+ default:
+ res = 0;
+ }
}
+ } else {
+ g_assert_not_reached();
}
return res;
bad_reg:
--
1.9.1
- [Qemu-devel] [PULL 00/36] target-arm queue, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 35/36] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 33/36] target-arm: Handle exception return from AArch64 to non-EL0 AArch32, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 31/36] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 28/36] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 20/36] target-arm: Add QOM property for Secure memory region, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision,
Peter Maydell <=
- [Qemu-devel] [PULL 23/36] target-arm: Support multiple address spaces in page table walks, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 29/36] target-arm: Move aarch64_cpu_do_interrupt() to helper.c, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 26/36] hw/arm/virt: Add always-on property to the virt board timer, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 30/36] target-arm: Use a single entry point for AArch64 and AArch32 exceptions, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 36/36] target-arm: Implement FPEXC32_EL2 system register, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 08/36] exec.c: Don't set cpu->as until cpu_address_space_init, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 18/36] memory: Add address_space_init_shareable(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 24/36] hw/arm/virt: Wire up memory region to CPUs explicitly, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 12/36] cpu: Add new asidx_from_attrs() method, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 16/36] exec.c: Use cpu_get_phys_page_attrs_debug, Peter Maydell, 2016/01/21