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[Qemu-devel] [PULL 14/64] target-ppc: add maddhd and maddhdu instruction
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 14/64] target-ppc: add maddhd and maddhdu instruction |
Date: |
Wed, 7 Sep 2016 20:28:53 +1000 |
From: Nikunj A Dadhania <address@hidden>
maddhd: Multiply-Add High Doubleword
maddhdu: Multiply-Add High Doubleword Unsigned
Above two instruction are dual form and differ by 1 bit
(31st bit)
Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and returns the higher dword in the target
register(RT).
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 488a105..0b21ea2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7749,6 +7749,29 @@ static void gen_maddld(DisasContext *ctx)
tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
tcg_temp_free_i64(t1);
}
+
+/* maddhd maddhdu */
+static void gen_maddhd_maddhdu(DisasContext *ctx)
+{
+ TCGv_i64 lo = tcg_temp_new_i64();
+ TCGv_i64 hi = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ if (Rc(ctx->opcode)) {
+ tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
+ cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_movi_i64(t1, 0);
+ } else {
+ tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
+ cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
+ }
+ tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
+ cpu_gpr[rC(ctx->opcode)], t1);
+ tcg_temp_free_i64(lo);
+ tcg_temp_free_i64(hi);
+ tcg_temp_free_i64(t1);
+}
#endif /* defined(TARGET_PPC64) */
GEN_VXFORM_NOA(vclzb, 1, 28)
@@ -10367,6 +10390,8 @@ GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800,
PPC_ALTIVEC),
GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
#if defined(TARGET_PPC64)
+GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
+ PPC2_ISA300),
GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
--
2.7.4
- [Qemu-devel] [PULL 19/64] ppc: Move DFP ops out of translate.c, (continued)
- [Qemu-devel] [PULL 19/64] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 33/64] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 28/64] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 12/64] target-ppc: add setb instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 35/64] ppc: Don't update NIP if not taking alignment exceptions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 26/64] ppc: FP exceptions are always precise, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 50/64] target-ppc: add vsrv instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 27/64] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 37/64] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 44/64] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/07
- [Qemu-devel] [PULL 14/64] target-ppc: add maddhd and maddhdu instruction,
David Gibson <=
- [Qemu-devel] [PULL 09/64] target-ppc: add cnttzd[.] instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 25/64] ppc: Don't update the NIP in floating point generated code, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 23/64] ppc: Make float_invalid_op_excp() pass the return address, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 31/64] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 38/64] ppc: Handle unconditional (always/never) traps at translation time, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 48/64] target-ppc: add vcmpnez[b, h, w][.] instructions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 60/64] ppc: Improve the exception helpers flags, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 54/64] hw/ppc: add a ppc_create_page_sizes_prop() helper routine, David Gibson, 2016/09/07