Re: [Qemu-devel] [PATCH v2 16/18] target-mips: Use the new extract op

[Yongbok Kim]

On 18/10/2016 16:10, Richard Henderson wrote:
> Use extract for EXT and DEXT.
> 
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target-mips/translate.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index d8dde7a..cf79aa4 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -4484,11 +4484,12 @@ static void gen_bitops (DisasContext *ctx, uint32_t 
> opc, int rt,
>          if (lsb + msb > 31) {
>              goto fail;
>          }
> -        tcg_gen_shri_tl(t0, t1, lsb);
>          if (msb != 31) {
> -            tcg_gen_andi_tl(t0, t0, (1U << (msb + 1)) - 1);
> +            tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
>          } else {
> -            tcg_gen_ext32s_tl(t0, t0);
> +            /* The two checks together imply that lsb == 0,
> +               so this is a simple sign-extension.  */
> +            tcg_gen_ext32s_tl(t0, t1);
>          }
>          break;
>  #if defined(TARGET_MIPS64)
> @@ -4503,10 +4504,7 @@ static void gen_bitops (DisasContext *ctx, uint32_t 
> opc, int rt,
>          if (lsb + msb > 63) {
>              goto fail;
>          }
> -        tcg_gen_shri_tl(t0, t1, lsb);
> -        if (msb != 63) {
> -            tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
> -        }
> +        tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
>          break;
>  #endif
>      case OPC_INS:
> 

Reviewed-by: Yongbok Kim <address@hidden>

Regards,
Yongbok