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Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instructio


From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction
Date: Wed, 14 Jun 2017 16:44:45 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.0

On 06/14/2017 01:00 PM, Thomas Huth wrote:
On 14.06.2017 09:56, David Hildenbrand wrote:
[...]
I think you should also mask the length with 0xffffffff if the PSW was
not in 64-bit mode? Or is this done automagically by the generated TCG
code already?

I was asking myself the same question, but it shouldn't really matter as
was we will be using a maximum of 4096, no?

Question is whether we can end up here somehow in 32-bit mode and the
upper part of the register is still != 0 ... something like 0x100000010
for example. Can we be sure that the upper half is always cleared if we
switch from 64-bit mode to the 32-bit mode before?

We don't currently have any length masking at the translate level.
Within mem_helper.c, we have wrap_length.


r~



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