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[Qemu-devel] [PULL 12/15] target/s390x: Clean up TB flag bits
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 12/15] target/s390x: Clean up TB flag bits |
Date: |
Fri, 23 Jun 2017 09:22:38 -0700 |
Most of the PSW bits that were being copied into TB->flags
are not relevant to translation. Removing those that are
unnecessary reduces the amount of translation required.
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/s390x/cpu.h | 24 +++++++++---------------
target/s390x/translate.c | 16 ++++++++--------
2 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 5b94ace..9faca04 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -346,19 +346,14 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
/* tb flags */
-#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
-#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
-#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
-#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
-#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
-#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
-#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
-#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
-#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
-#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
-#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
-#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
-#define FLAG_MASK_32 0x00001000
+#define FLAG_MASK_PSW_SHIFT 31
+#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
+ | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
/* Control register 0 bits */
#define CR0_LOWPROT 0x0000000010000000ULL
@@ -416,8 +411,7 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env,
target_ulong *pc,
{
*pc = env->psw.addr;
*cs_base = env->ex_value;
- *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
- ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
+ *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
}
#define MAX_ILEN 6
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index a3414c0..df3fefa 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -323,11 +323,11 @@ static inline uint64_t ld_code4(CPUS390XState *env,
uint64_t pc)
static int get_mem_index(DisasContext *s)
{
switch (s->tb->flags & FLAG_MASK_ASC) {
- case PSW_ASC_PRIMARY >> 32:
+ case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
return 0;
- case PSW_ASC_SECONDARY >> 32:
+ case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
return 1;
- case PSW_ASC_HOME >> 32:
+ case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
return 2;
default:
tcg_abort();
@@ -387,7 +387,7 @@ static inline void gen_trap(DisasContext *s)
#ifndef CONFIG_USER_ONLY
static void check_privileged(DisasContext *s)
{
- if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
+ if (s->tb->flags & FLAG_MASK_PSTATE) {
gen_program_exception(s, PGM_PRIVILEGED);
}
}
@@ -2932,20 +2932,20 @@ static ExitStatus op_mov2e(DisasContext *s, DisasOps *o)
o->g_in2 = false;
switch (s->tb->flags & FLAG_MASK_ASC) {
- case PSW_ASC_PRIMARY >> 32:
+ case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 0);
break;
- case PSW_ASC_ACCREG >> 32:
+ case PSW_ASC_ACCREG >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 1);
break;
- case PSW_ASC_SECONDARY >> 32:
+ case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
if (b2) {
tcg_gen_ld32u_i64(ar1, cpu_env, offsetof(CPUS390XState,
aregs[b2]));
} else {
tcg_gen_movi_i64(ar1, 0);
}
break;
- case PSW_ASC_HOME >> 32:
+ case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 2);
break;
}
--
2.9.4
- [Qemu-devel] [PULL 01/15] target/s390x: Map existing FAC_* names to S390_FEAT_* names, (continued)
- [Qemu-devel] [PULL 01/15] target/s390x: Map existing FAC_* names to S390_FEAT_* names, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 02/15] target/s390x: change PSW_SHIFT_KEY, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 05/15] target/s390x: Implement load-on-condition-2 insns, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 04/15] target/s390x: Mark FPSEH facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 03/15] target/s390x: implement mvcos instruction, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 07/15] target/s390x: Mark STFLE_53 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 09/15] target/s390x: Implement processor-assist insn, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 08/15] target/s390x: Implement execution-hint insns, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 10/15] target/s390x: Mark STFLE_49 facility as available, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 11/15] target/s390x: Finish implementing ETF2-ENH, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 12/15] target/s390x: Clean up TB flag bits,
Richard Henderson <=
- [Qemu-devel] [PULL 13/15] target/s390x: Indicate and check for local tlb clearing, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 14/15] target/s390x: Improve heuristic for ipte, Richard Henderson, 2017/06/23
- [Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction, Richard Henderson, 2017/06/23
- Re: [Qemu-devel] [PULL 00/15] Queued target/s390x patches, Peter Maydell, 2017/06/26