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Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation


From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation
Date: Tue, 13 Feb 2018 14:10:20 -0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0

On 02/13/2018 01:55 PM, Emilio G. Cota wrote:
> On Thu, Feb 08, 2018 at 14:28:34 +1300, Michael Clark wrote:
>> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
>> RISC-V code generator has complete coverage for the Base ISA v2.2,
>> Privileged ISA v1.9.1 and Privileged ISA v1.10:
>>
>> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
>> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
>> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
>>
>> Reviewed-by: Richard Henderson <address@hidden>
>> Signed-off-by: Michael Clark <address@hidden>
>> ---
> (snip)
>> +++ b/target/riscv/translate.c
> (snip)
>> +enum {
>> +    BS_NONE     = 0, /* When seen outside of translation while loop, 
>> indicates
>> +                     need to exit tb due to end of page. */
>> +    BS_STOP     = 1, /* Need to exit tb for syscall, sret, etc. */
> 
> Are we planning to use BS_STOP in the future? I see it has no setters,
> although we check for it in gen_intermediate_code:

No, but the whole port should be converted to exec/translator.h, which defines
DisasJumpType.  Not something I'm going to require on initial submission until
we've gotten most of the other targets cleaned up.


r~




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