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[Qemu-devel] [PATCH 31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bo
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH 31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader |
Date: |
Wed, 20 Jun 2018 13:06:16 +0100 |
From: Paul Burton <address@hidden>
Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that
they are setup in the MIPS32 bootloader. This is necessary for Linux to
be able to access peripherals, including the UART.
Signed-off-by: Paul Burton <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
---
hw/mips/mips_malta.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 39f4c5b..c4139d6 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -663,6 +663,79 @@ static void write_bootloader_nanomips(uint8_t *base,
int64_t run_addr,
/* lui a3,%hi(loaderparams.ram_low_size) */
stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
/* ori a3,a3,%lo(loaderparams.ram_low_size) */
+
+ /* Load BAR registers as done by YAMON */
+ stw_p(p++, 0xe040); stw_p(p++, 0x0681);
+ /* lui t1, %hi(0xb4000000) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
+ /* lui t0, %hi(0xdf000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x00df);
+ /* addiu[32] t0, $0, 0xdf */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9068);
+ /* sw t0, 0x68(t1) */
+
+ stw_p(p++, 0xe040); stw_p(p++, 0x077d);
+ /* lui t1, %hi(0xbbe00000) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0801);
+ /* lui t0, %hi(0xc0000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
+ /* addiu[32] t0, $0, 0xc0 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9048);
+ /* sw t0, 0x48(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0800);
+ /* lui t0, %hi(0x40000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x0040);
+ /* addiu[32] t0, $0, 0x40 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9050);
+ /* sw t0, 0x50(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0001);
+ /* lui t0, %hi(0x80000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x0080);
+ /* addiu[32] t0, $0, 0x80 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9058);
+ /* sw t0, 0x58(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
+ /* lui t0, %hi(0x3f000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x003f);
+ /* addiu[32] t0, $0, 0x3f */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9060);
+ /* sw t0, 0x60(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0821);
+ /* lui t0, %hi(0xc1000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
+ /* addiu[32] t0, $0, 0xc1 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9080);
+ /* sw t0, 0x80(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
+ /* lui t0, %hi(0x5e000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x005e);
+ /* addiu[32] t0, $0, 0x5e */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9088);
+ /* sw t0, 0x88(t1) */
+
stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
stw_p(p++, NM_HI2(kernel_entry));
/* lui t9,%hi(kernel_entry) */
--
1.9.1
- Re: [Qemu-devel] [PATCH 22/35] target/mips: Fix data type for offset, (continued)
- [Qemu-devel] [PATCH 23/35] target/mips: Update BadInstr{P} regs on nanoMIPS, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX register, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 25/35] target/mips: Config3.ISAOnExc is read only in nanoMIPS, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 26/35] target/mips: Fix nanoMIPS exception_resume_pc, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 27/35] target/mips: Fix nanoMIPS set_hflags_for_handler, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 28/35] target/mips: Fix nanoMIPS set_pc, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 29/35] target/mips: Fix ERET/ERETNC can cause ADEL exception, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 30/35] hw/mips: Add basic nanoMIPS boot code, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader,
Yongbok Kim <=
- [Qemu-devel] [PATCH 32/35] hw/mips: Fix semihosting argument passing for nanoMIPS bare metal, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 33/35] target/mips: Fix gdbstub to read/write 64 bit FP registers, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 34/35] target/mips: Disable gdbstub nanoMIPS ISA bit, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 35/35] target/mips: Add I7200 CPU, Yongbok Kim, 2018/06/20
- Re: [Qemu-devel] [PATCH 00/35] nanoMIPS, Philippe Mathieu-Daudé, 2018/06/22
- Re: [Qemu-devel] [PATCH 00/35] nanoMIPS, Aleksandar Markovic, 2018/06/22