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[Qemu-devel] [PATCH 35/35] target/mips: Add I7200 CPU
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH 35/35] target/mips: Add I7200 CPU |
Date: |
Wed, 20 Jun 2018 13:06:20 +0100 |
From: Stefan Markovic <address@hidden>
Add I7200 CPU
Reference:
https://www.mips.com/products/warrior/i-class-i7200-multiprocessor-core/
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/translate_init.inc.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index c7ba6ee..262ff29 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -449,6 +449,43 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ .name = "I7200",
+ .CP0_PRid = 0x00010000,
+ .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
+ (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
+ (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
+ (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_CMGCR) | (1 << CP0C3_BI) |
+ (3 << CP0C3_MMAR) | (1 << CP0C3_ISA_ON_EXC) |
+ (1 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) |
+ (1 << CP0C3_VInt) | (1U << CP0C3_M) | (1 << CP0C3_MT),
+ .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
+ (2 << CP0C4_IE) | (1U << CP0C4_M),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
+ (1 << CP0C5_UFE),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3058FF1F,
+ .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
+ (1U << CP0PG_RIE),
+ .CP0_PageGrain_rw_bitmask = 0,
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_NANOMIPS32 | ASE_MICROMIPS,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#if defined(TARGET_MIPS64)
{
.name = "R4000",
--
1.9.1
- [Qemu-devel] [PATCH 27/35] target/mips: Fix nanoMIPS set_hflags_for_handler, (continued)
- [Qemu-devel] [PATCH 27/35] target/mips: Fix nanoMIPS set_hflags_for_handler, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 28/35] target/mips: Fix nanoMIPS set_pc, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 29/35] target/mips: Fix ERET/ERETNC can cause ADEL exception, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 30/35] hw/mips: Add basic nanoMIPS boot code, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 32/35] hw/mips: Fix semihosting argument passing for nanoMIPS bare metal, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 33/35] target/mips: Fix gdbstub to read/write 64 bit FP registers, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 34/35] target/mips: Disable gdbstub nanoMIPS ISA bit, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 35/35] target/mips: Add I7200 CPU,
Yongbok Kim <=
- Re: [Qemu-devel] [PATCH 00/35] nanoMIPS, Philippe Mathieu-Daudé, 2018/06/22
- Re: [Qemu-devel] [PATCH 00/35] nanoMIPS, Aleksandar Markovic, 2018/06/22