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[Qemu-devel] [PULL 51/55] target/arm: Fix SVE signed division vs x86 ove
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 51/55] target/arm: Fix SVE signed division vs x86 overflow exception |
Date: |
Fri, 29 Jun 2018 15:53:43 +0100 |
From: Richard Henderson <address@hidden>
We already check for the same condition within the normal integer
sdiv and sdiv64 helpers. Use a slightly different formation that
does not require deducing the expression type.
Fixes: f97cfd596ed
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: reworded a comment]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/sve_helper.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 790cbacd146..a03ca773542 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -369,7 +369,17 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg,
uint32_t desc) \
#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
#define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N))
#define DO_MUL(N, M) (N * M)
-#define DO_DIV(N, M) (M ? N / M : 0)
+
+
+/*
+ * We must avoid the C undefined behaviour cases: division by
+ * zero and signed division of INT_MIN by -1. Both of these
+ * have architecturally defined required results for Arm.
+ * We special case all signed divisions by -1 to avoid having
+ * to deduce the minimum integer for the type involved.
+ */
+#define DO_SDIV(N, M) (unlikely(M == 0) ? 0 : unlikely(M == -1) ? -N : N / M)
+#define DO_UDIV(N, M) (unlikely(M == 0) ? 0 : N / M)
DO_ZPZZ(sve_and_zpzz_b, uint8_t, H1, DO_AND)
DO_ZPZZ(sve_and_zpzz_h, uint16_t, H1_2, DO_AND)
@@ -477,11 +487,11 @@ DO_ZPZZ(sve_umulh_zpzz_h, uint16_t, H1_2, do_mulh_h)
DO_ZPZZ(sve_umulh_zpzz_s, uint32_t, H1_4, do_mulh_s)
DO_ZPZZ_D(sve_umulh_zpzz_d, uint64_t, do_umulh_d)
-DO_ZPZZ(sve_sdiv_zpzz_s, int32_t, H1_4, DO_DIV)
-DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_DIV)
+DO_ZPZZ(sve_sdiv_zpzz_s, int32_t, H1_4, DO_SDIV)
+DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_SDIV)
-DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_DIV)
-DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV)
+DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_UDIV)
+DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_UDIV)
/* Note that all bits of the shift are significant
and not modulo the element size. */
--
2.17.1
- [Qemu-devel] [PULL 28/55] target/arm: Implement SVE floating-point trig multiply-add coefficient, (continued)
- [Qemu-devel] [PULL 28/55] target/arm: Implement SVE floating-point trig multiply-add coefficient, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 35/55] target/arm: Implement SVE fp complex multiply add, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 38/55] target/arm: Implement SVE dot product (vectors), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 43/55] i.mx7d: Remove unused header files, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 44/55] i.mx7d: Change SRC unimplemented device name from sdma to src, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 34/55] target/arm: Implement SVE floating-point complex add, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 41/55] target/arm: Implement ARMv8.2-DotProd, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 48/55] target/arm: Mark PMINTENSET accesses as possibly doing IO, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 49/55] sd: Don't trace SDRequest crc field, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 45/55] i.mx7d: Change IRQ number type from hwaddr to int, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 51/55] target/arm: Fix SVE signed division vs x86 overflow exception,
Peter Maydell <=
- [Qemu-devel] [PULL 52/55] target/arm: Fix SVE system register access checks, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 47/55] target/arm: Remove redundant DIV detection for KVM, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 31/55] target/arm: Implement SVE floating-point round to integral value, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 40/55] target/arm: Enable SVE for aarch64-linux-user, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 42/55] target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-space, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 46/55] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 53/55] target/arm: Prune a57 features from max, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 54/55] target/arm: Prune a15 features from max, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 55/55] target/arm: Add ID_ISAR6, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 50/55] sdcard: Use the ldst API, Peter Maydell, 2018/06/29