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[Qemu-devel] [PULL 46/55] target/arm: Add ARM_FEATURE_V7VE for v7 Virtua
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 46/55] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions |
Date: |
Fri, 29 Jun 2018 15:53:38 +0100 |
From: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 1 +
target/arm/cpu.c | 21 ++++++++++++++-------
target/arm/kvm32.c | 8 ++++----
3 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6a8441c2dd6..7ac909448ea 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1442,6 +1442,7 @@ enum arm_features {
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
ARM_FEATURE_THUMB2EE,
ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
+ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
ARM_FEATURE_V4T,
ARM_FEATURE_V5,
ARM_FEATURE_STRONGARM,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index aa62315cea2..4584cd01bc1 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -800,9 +800,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
/* Some features automatically imply others: */
if (arm_feature(env, ARM_FEATURE_V8)) {
- set_feature(env, ARM_FEATURE_V7);
+ set_feature(env, ARM_FEATURE_V7VE);
+ }
+ if (arm_feature(env, ARM_FEATURE_V7VE)) {
+ /* v7 Virtualization Extensions. In real hardware this implies
+ * EL2 and also the presence of the Security Extensions.
+ * For QEMU, for backwards-compatibility we implement some
+ * CPUs or CPU configs which have no actual EL2 or EL3 but do
+ * include the various other features that V7VE implies.
+ * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
+ * Security Extensions is ARM_FEATURE_EL3.
+ */
set_feature(env, ARM_FEATURE_ARM_DIV);
set_feature(env, ARM_FEATURE_LPAE);
+ set_feature(env, ARM_FEATURE_V7);
}
if (arm_feature(env, ARM_FEATURE_V7)) {
set_feature(env, ARM_FEATURE_VAPA);
@@ -1524,15 +1535,13 @@ static void cortex_a7_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
cpu->dtb_compatible = "arm,cortex-a7";
- set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_V7VE);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
- set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_LPAE);
set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
cpu->midr = 0x410fc075;
@@ -1569,15 +1578,13 @@ static void cortex_a15_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
cpu->dtb_compatible = "arm,cortex-a15";
- set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_V7VE);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
- set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_LPAE);
set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index 1740cda47da..fb9ea37a318 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -98,12 +98,12 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
/* Now we've retrieved all the register information we can
* set the feature bits based on the ID register fields.
* We can assume any KVM supporting CPU is at least a v7
- * with VFPv3, LPAE and the generic timers; this in turn implies
- * most of the other feature bits, but a few must be tested.
+ * with VFPv3, virtualization extensions, and the generic
+ * timers; this in turn implies most of the other feature
+ * bits, but a few must be tested.
*/
- set_feature(&features, ARM_FEATURE_V7);
+ set_feature(&features, ARM_FEATURE_V7VE);
set_feature(&features, ARM_FEATURE_VFP3);
- set_feature(&features, ARM_FEATURE_LPAE);
set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
switch (extract32(id_isar0, 24, 4)) {
--
2.17.1
- [Qemu-devel] [PULL 41/55] target/arm: Implement ARMv8.2-DotProd, (continued)
- [Qemu-devel] [PULL 41/55] target/arm: Implement ARMv8.2-DotProd, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 48/55] target/arm: Mark PMINTENSET accesses as possibly doing IO, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 49/55] sd: Don't trace SDRequest crc field, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 45/55] i.mx7d: Change IRQ number type from hwaddr to int, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 51/55] target/arm: Fix SVE signed division vs x86 overflow exception, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 52/55] target/arm: Fix SVE system register access checks, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 47/55] target/arm: Remove redundant DIV detection for KVM, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 31/55] target/arm: Implement SVE floating-point round to integral value, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 40/55] target/arm: Enable SVE for aarch64-linux-user, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 42/55] target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-space, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 46/55] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions,
Peter Maydell <=
- [Qemu-devel] [PULL 53/55] target/arm: Prune a57 features from max, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 54/55] target/arm: Prune a15 features from max, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 55/55] target/arm: Add ID_ISAR6, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 50/55] sdcard: Use the ldst API, Peter Maydell, 2018/06/29
- Re: [Qemu-devel] [PULL 00/55] target-arm queue, Peter Maydell, 2018/06/30