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[Qemu-devel] [PULL 55/55] target/arm: Add ID_ISAR6
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 55/55] target/arm: Add ID_ISAR6 |
Date: |
Fri, 29 Jun 2018 15:53:47 +0100 |
From: Richard Henderson <address@hidden>
This register was added to aa32 state by ARMv8.2.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 1 +
target/arm/cpu.c | 4 ++++
target/arm/cpu64.c | 2 ++
target/arm/helper.c | 5 ++---
4 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7ac909448ea..e310ffc29d2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -813,6 +813,7 @@ struct ARMCPU {
uint32_t id_isar3;
uint32_t id_isar4;
uint32_t id_isar5;
+ uint32_t id_isar6;
uint64_t id_aa64pfr0;
uint64_t id_aa64pfr1;
uint64_t id_aa64dfr0;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 646b122e163..82ff450f9a7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1273,6 +1273,7 @@ static void cortex_m3_initfn(Object *obj)
cpu->id_isar3 = 0x01111110;
cpu->id_isar4 = 0x01310102;
cpu->id_isar5 = 0x00000000;
+ cpu->id_isar6 = 0x00000000;
}
static void cortex_m4_initfn(Object *obj)
@@ -1299,6 +1300,7 @@ static void cortex_m4_initfn(Object *obj)
cpu->id_isar3 = 0x01111110;
cpu->id_isar4 = 0x01310102;
cpu->id_isar5 = 0x00000000;
+ cpu->id_isar6 = 0x00000000;
}
static void cortex_m33_initfn(Object *obj)
@@ -1327,6 +1329,7 @@ static void cortex_m33_initfn(Object *obj)
cpu->id_isar3 = 0x01111131;
cpu->id_isar4 = 0x01310132;
cpu->id_isar5 = 0x00000000;
+ cpu->id_isar6 = 0x00000000;
cpu->clidr = 0x00000000;
cpu->ctr = 0x8000c000;
}
@@ -1377,6 +1380,7 @@ static void cortex_r5_initfn(Object *obj)
cpu->id_isar3 = 0x01112131;
cpu->id_isar4 = 0x0010142;
cpu->id_isar5 = 0x0;
+ cpu->id_isar6 = 0x0;
cpu->mp_is_up = true;
cpu->pmsav7_dregion = 16;
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 8040493d5cf..d0581d59d82 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -139,6 +139,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->id_isar3 = 0x01112131;
cpu->id_isar4 = 0x00011142;
cpu->id_isar5 = 0x00011121;
+ cpu->id_isar6 = 0;
cpu->id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106;
cpu->pmceid0 = 0x00000000;
@@ -199,6 +200,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->id_isar3 = 0x01112131;
cpu->id_isar4 = 0x00011142;
cpu->id_isar5 = 0x00011121;
+ cpu->id_isar6 = 0;
cpu->id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106;
cpu->id_aa64isar0 = 0x00011120;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ae70b874c71..a2ac96084e7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4872,11 +4872,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_mmfr4 },
- /* 7 is as yet unallocated and must RAZ */
- { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
+ { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = 0 },
+ .resetvalue = cpu->id_isar6 },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, v6_idregs);
--
2.17.1
- [Qemu-devel] [PULL 45/55] i.mx7d: Change IRQ number type from hwaddr to int, (continued)
- [Qemu-devel] [PULL 45/55] i.mx7d: Change IRQ number type from hwaddr to int, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 51/55] target/arm: Fix SVE signed division vs x86 overflow exception, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 52/55] target/arm: Fix SVE system register access checks, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 47/55] target/arm: Remove redundant DIV detection for KVM, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 31/55] target/arm: Implement SVE floating-point round to integral value, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 40/55] target/arm: Enable SVE for aarch64-linux-user, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 42/55] target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-space, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 46/55] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 53/55] target/arm: Prune a57 features from max, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 54/55] target/arm: Prune a15 features from max, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 55/55] target/arm: Add ID_ISAR6,
Peter Maydell <=
- [Qemu-devel] [PULL 50/55] sdcard: Use the ldst API, Peter Maydell, 2018/06/29
- Re: [Qemu-devel] [PULL 00/55] target-arm queue, Peter Maydell, 2018/06/30