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[Qemu-devel] [PULL 19/25] nvic: Expose NMI line
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/25] nvic: Expose NMI line |
Date: |
Mon, 20 Aug 2018 11:32:06 +0100 |
On real v7M hardware, the NMI line is an externally visible signal
that an SoC or board can toggle to assert an NMI. Expose it in
our QEMU NVIC and armv7m container objects so that a board model
can wire it up if it needs to.
In particular, the MPS2 watchdog is wired to NMI.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/arm/armv7m.c | 1 +
hw/intc/armv7m_nvic.c | 19 +++++++++++++++++++
hw/intc/trace-events | 1 +
3 files changed, 21 insertions(+)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 878613994d2..4bf9131b81e 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -202,6 +202,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
*/
qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
/* Wire the NVIC up to the CPU */
sbd = SYS_BUS_DEVICE(&s->nvic);
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 351b69ab40b..0d816fdd2cc 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -774,6 +774,24 @@ static void set_irq_level(void *opaque, int n, int level)
}
}
+/* callback when external NMI line is changed */
+static void nvic_nmi_trigger(void *opaque, int n, int level)
+{
+ NVICState *s = opaque;
+
+ trace_nvic_set_nmi_level(level);
+
+ /*
+ * The architecture doesn't specify whether NMI should share
+ * the normal-interrupt behaviour of being resampled on
+ * exception handler return. We choose not to, so just
+ * set NMI pending here and don't track the current level.
+ */
+ if (level) {
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
+ }
+}
+
static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
{
ARMCPU *cpu = s->cpu;
@@ -2382,6 +2400,7 @@ static void armv7m_nvic_instance_init(Object *obj)
qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger",
M_REG_NUM_BANKS);
+ qdev_init_gpio_in_named(dev, nvic_nmi_trigger, "NMI", 1);
}
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 81c7c399f7d..7769869a135 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -192,6 +192,7 @@ nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge
IRQ: %d now active (pr
nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d:
targets_secure: %d"
nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"
nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
+nvic_set_nmi_level(int level) "NVIC external NMI level set to %d"
nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg
read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg
write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
--
2.18.0
- [Qemu-devel] [PULL 08/25] target/arm: Implement AArch32 Hyp FARs, (continued)
- [Qemu-devel] [PULL 08/25] target/arm: Implement AArch32 Hyp FARs, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 11/25] target/arm: Implement AArch32 ERET instruction, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 10/25] target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked), Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 13/25] sdhci: add i.MX SD Stable Clock bit, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 12/25] hw/arm/virt: Add virt-3.1 machine type, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 17/25] hw/timer/m48t59: Move away from old_mmio accessors, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 14/25] hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr code, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 09/25] target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 16/25] hw/misc: Remove mmio_interface device, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 19/25] nvic: Expose NMI line,
Peter Maydell <=
- [Qemu-devel] [PULL 02/25] docs/generic-loader: mention U-Boot and Intel HEX executable formats, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 01/25] target/arm: Fix crash on conditional instruction in an IT block, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 15/25] memory: Remove MMIO request_ptr APIs, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 18/25] hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 22/25] hw/dma/pl080: Don't use CPU address space for DMA accesses, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 23/25] hw/dma/pl080: Provide device reset function, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 21/25] hw/dma/pl080: Support all three interrupt lines, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 20/25] hw/dma/pl080: Allow use as embedded-struct device, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 24/25] hw/dma/pl080: Correct bug in register address decode logic, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 25/25] hw/dma/pl080: Remove hw_error() if DMA is enabled, Peter Maydell, 2018/08/20